From 42d2e470451d10420f70cb263377cc5ebaab02f9 Mon Sep 17 00:00:00 2001 From: Scott Collyer Date: Sat, 30 Jul 2022 17:11:39 -0700 Subject: rex: Add support for power sequencing This CL adds the config options, power signals nodes, and support functions required to support power sequencing. BRANCH=none BUG=b:240434243 TEST=zmake build rex Signed-off-by: Scott Collyer Change-Id: I932995ddac4831bc0be3efefd7d345beef122178 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3798471 Reviewed-by: Vijay P Hiremath Tested-by: Scott Collyer Reviewed-by: Fabio Baltieri Commit-Queue: Scott Collyer --- zephyr/projects/rex/power_signals.dts | 145 ++++++++++++++++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 zephyr/projects/rex/power_signals.dts (limited to 'zephyr/projects/rex/power_signals.dts') diff --git a/zephyr/projects/rex/power_signals.dts b/zephyr/projects/rex/power_signals.dts new file mode 100644 index 0000000000..1df4a4bb0c --- /dev/null +++ b/zephyr/projects/rex/power_signals.dts @@ -0,0 +1,145 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <3>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP1800_S5/PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpiob 6 0>; + output; + }; + pwr-pg-ec-rsmrst-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpioe 2 0>; + interrupt-flags = ; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioa 6 0>; + output; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpioa 5 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpiob 0 GPIO_OPEN_DRAIN>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + gpios = <&gpiof 4 0>; + interrupt-flags = ; + }; +}; + +/* + * Because the power signals directly reference the GPIOs, + * the corresponding named-gpios need to have no-auto-init set. + */ + /* pwr-en-pp3300-s5 */ +&gpio_en_s5_rails { + no-auto-init; +}; + +/* pwr-pg-ec-rsmrst-od */ +&gpio_seq_ec_rsmrst_odl{ + no-auto-init; +}; + +/* pwr-ec-pch-rsmrst-odl */ +&gpio_ec_soc_rsmrst_l{ + no-auto-init; +}; + +/* pwr-pch-pwrok */ +&gpio_soc_pwrok{ + no-auto-init; +}; + +/* pwr-ec-pch-sys-pwrok */ +&gpio_sys_pwrok{ + no-auto-init; +}; + +/* pwr-sys-rst-l */ +&gpio_sys_rst_odl{ + no-auto-init; +}; + +/* pwr-slp-s0-l */ +&gpio_sys_slp_s0ix_3v3_l{ + no-auto-init; +}; + +/* pwr-slp-s3-l */ +&gpio_slp_s3_ls_l{ + no-auto-init; +}; + +/* pwr-all-sys-pwrgd */ +&gpio_seq_ec_all_sys_pg{ + no-auto-init; +}; + -- cgit v1.2.1 From 9d4d0c455faa7fe72bafd26da6142b961bc836c9 Mon Sep 17 00:00:00 2001 From: Scott Collyer Date: Wed, 10 Aug 2022 12:18:43 -0700 Subject: rex: Use VW for sleep S3 and enable EC_SYSTEM_UNLOCKED This CL fixes an issue where the config option was set to use VW for sleep S3, but the power_signal node did not reflect this. In addition, CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED was added and CONFIG_PLATFORM_EC_BRINGUP was removed to allow for the AP to boot up automatically. BRANCH=none BUG=b:240434243 TEST=zmake build rex Signed-off-by: Scott Collyer Change-Id: I83c939d5637736a7460f8f5388ebcaddf389bd35 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3823913 Reviewed-by: Fabio Baltieri Reviewed-by: Madhu P Tested-by: Scott Collyer Reviewed-by: Li1 Feng Commit-Queue: Scott Collyer --- zephyr/projects/rex/power_signals.dts | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'zephyr/projects/rex/power_signals.dts') diff --git a/zephyr/projects/rex/power_signals.dts b/zephyr/projects/rex/power_signals.dts index 1df4a4bb0c..bf96ead2af 100644 --- a/zephyr/projects/rex/power_signals.dts +++ b/zephyr/projects/rex/power_signals.dts @@ -65,11 +65,18 @@ interrupt-flags = ; }; pwr-slp-s3-l { - compatible = "intel,ap-pwrseq-gpio"; + compatible = "intel,ap-pwrseq-vw"; dbg-label = "SLP_S3_L input from PCH"; enum-name = "PWR_SLP_S3"; - gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; - interrupt-flags = ; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; +/* + * TODO: Initially, use virtual wire for sleep S3 signal instead of + * of the GPIO signal which also exists. + * compatible = "intel,ap-pwrseq-gpio"; + * gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; + * interrupt-flags = ; + */ }; pwr-slp-s4 { compatible = "intel,ap-pwrseq-vw"; -- cgit v1.2.1 From 01e90e3e76e5d11e214be6d2e4da11defc450638 Mon Sep 17 00:00:00 2001 From: Scott Collyer Date: Wed, 24 Aug 2022 11:57:16 -0700 Subject: rex: Make SOC_PWROK/SYS_PWROK signals TTL instead of OD Both SOC_PWROK and SYS_PWROK signals are designed to be TTL outputs, but they were being configured as open drain outputs in their power signals node. In addition, this CL adds an internal pullup to SEQ_EC_ALL_SYS_PG as a work-around for the missing pullup on the board. Lastly, for the gpio flags field, 0 was replaces with GPIO_ACTIVE_HIGH for readability. BRANCH=none BUG=b:243638916 TEST=zmake build rex Signed-off-by: Scott Collyer Change-Id: Ifd7f88b863d5468fbcfa979d23b0071f429903d1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3855156 Tested-by: Scott Collyer Commit-Queue: Scott Collyer Reviewed-by: Fabio Baltieri Reviewed-by: Vijay P Hiremath --- zephyr/projects/rex/power_signals.dts | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'zephyr/projects/rex/power_signals.dts') diff --git a/zephyr/projects/rex/power_signals.dts b/zephyr/projects/rex/power_signals.dts index bf96ead2af..a4cc3cb5ef 100644 --- a/zephyr/projects/rex/power_signals.dts +++ b/zephyr/projects/rex/power_signals.dts @@ -19,42 +19,42 @@ compatible = "intel,ap-pwrseq-gpio"; dbg-label = "PP1800_S5/PP3300_S5 enable output to LS"; enum-name = "PWR_EN_PP3300_A"; - gpios = <&gpiob 6 0>; + gpios = <&gpiob 6 GPIO_ACTIVE_HIGH>; output; }; pwr-pg-ec-rsmrst-od { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "RSMRST power good from regulator"; enum-name = "PWR_RSMRST"; - gpios = <&gpioe 2 0>; + gpios = <&gpioe 2 GPIO_ACTIVE_HIGH>; interrupt-flags = ; }; pwr-ec-pch-rsmrst-odl { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "RSMRST output to PCH"; enum-name = "PWR_EC_PCH_RSMRST"; - gpios = <&gpioa 6 0>; + gpios = <&gpioa 6 GPIO_ACTIVE_HIGH>; output; }; pwr-pch-pwrok { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "PCH_PWROK output to PCH"; enum-name = "PWR_PCH_PWROK"; - gpios = <&gpioa 5 GPIO_OPEN_DRAIN>; + gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>; output; }; pwr-ec-pch-sys-pwrok { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "SYS_PWROK output to PCH"; enum-name = "PWR_EC_PCH_SYS_PWROK"; - gpios = <&gpiob 0 GPIO_OPEN_DRAIN>; + gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>; output; }; pwr-sys-rst-l { compatible = "intel,ap-pwrseq-gpio"; dbg-label = "SYS_RESET# output to PCH"; enum-name = "PWR_SYS_RST"; - gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + gpios = <&gpioc 5 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; output; }; pwr-slp-s0-l { @@ -96,7 +96,7 @@ compatible = "intel,ap-pwrseq-gpio"; dbg-label = "all power good"; enum-name = "PWR_ALL_SYS_PWRGD"; - gpios = <&gpiof 4 0>; + gpios = <&gpiof 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; interrupt-flags = ; }; }; -- cgit v1.2.1 From 71b2ef709dcb14260f5fdaa3ab4ced005a29fb46 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 12 Sep 2022 14:54:36 -0400 Subject: Update license boilerplate text in source code files Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b Signed-off-by: Mike Frysinger Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203 Reviewed-by: Jeremy Bettis Reviewed-by: Jack Rosenthal --- zephyr/projects/rex/power_signals.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'zephyr/projects/rex/power_signals.dts') diff --git a/zephyr/projects/rex/power_signals.dts b/zephyr/projects/rex/power_signals.dts index a4cc3cb5ef..860c316795 100644 --- a/zephyr/projects/rex/power_signals.dts +++ b/zephyr/projects/rex/power_signals.dts @@ -1,4 +1,4 @@ -/* Copyright 2022 The ChromiumOS Authors. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ -- cgit v1.2.1