/* Copyright 2014 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * * Register map for NPCX processor */ #ifndef __CROS_EC_REGISTERS_H #define __CROS_EC_REGISTERS_H #include "common.h" #include "compile_time_macros.h" #include "clock_chip.h" /******************************************************************************/ /* * Macro Functions */ /* Bit functions */ #define SET_BIT(reg, bit) ((reg) |= (0x1 << (bit))) #define CLEAR_BIT(reg, bit) ((reg) &= (~(0x1 << (bit)))) #define IS_BIT_SET(reg, bit) (((reg) >> (bit)) & (0x1)) #define UPDATE_BIT(reg, bit, cond) { if (cond) \ SET_BIT(reg, bit); \ else \ CLEAR_BIT(reg, bit); } /* Field functions */ #define GET_POS_FIELD(pos, size) pos #define GET_SIZE_FIELD(pos, size) size #define FIELD_POS(field) GET_POS_##field #define FIELD_SIZE(field) GET_SIZE_##field /* Read field functions */ #define GET_FIELD(reg, field) \ _GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field)) #define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1)) /* Write field functions */ #define SET_FIELD(reg, field, value) \ _SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value) #define _SET_FIELD_(reg, f_pos, f_size, value) \ ((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \ | ((value) << (f_pos))) /******************************************************************************/ /* * NPCX (Nuvoton M4 EC) Register Definitions */ /* Global Definition */ #define I2C_7BITS_ADDR 0 /* Switcher of features */ #define SUPPORT_LCT 1 #define SUPPORT_WDG 1 #define SUPPORT_P80_SEG 0 /* Note: it uses KSO10 & KSO11 */ /* Switcher of debugging */ #define DEBUG_GPIO 0 #define DEBUG_I2C 0 #define DEBUG_TMR 0 #define DEBUG_WDG 0 #define DEBUG_FAN 0 #define DEBUG_PWM 0 #define DEBUG_SPI 0 #define DEBUG_FLH 0 #define DEBUG_PECI 0 #define DEBUG_SHI 0 #define DEBUG_CLK 0 #define DEBUG_LPC 0 #define DEBUG_ESPI 0 #define DEBUG_CEC 0 #define DEBUG_SIB 0 #define DEBUG_PS2 0 /* Modules Map */ #define NPCX_ESPI_BASE_ADDR 0x4000A000 #define NPCX_MDC_BASE_ADDR 0x4000C000 #define NPCX_PMC_BASE_ADDR 0x4000D000 #define NPCX_SIB_BASE_ADDR 0x4000E000 #define NPCX_SHI_BASE_ADDR 0x4000F000 #define NPCX_SHM_BASE_ADDR 0x40010000 #define NPCX_GDMA_BASE_ADDR 0x40011000 #define NPCX_FIU_BASE_ADDR 0x40020000 #define NPCX_KBSCAN_REGS_BASE 0x400A3000 #define NPCX_WOV_BASE_ADDR 0x400A4000 #define NPCX_APM_BASE_ADDR 0x400A4800 #define NPCX_GLUE_REGS_BASE 0x400A5000 #define NPCX_BBRAM_BASE_ADDR 0x400AF000 #define NPCX_PS2_BASE_ADDR 0x400B1000 #define NPCX_HFCG_BASE_ADDR 0x400B5000 #define NPCX_LFCG_BASE_ADDR 0x400B5100 #define NPCX_FMUL2_BASE_ADDR 0x400B5200 #define NPCX_MTC_BASE_ADDR 0x400B7000 #define NPCX_MSWC_BASE_ADDR 0x400C1000 #define NPCX_SCFG_BASE_ADDR 0x400C3000 #define NPCX_KBC_BASE_ADDR 0x400C7000 #define NPCX_ADC_BASE_ADDR 0x400D1000 #define NPCX_SPI_BASE_ADDR 0x400D2000 #define NPCX_PECI_BASE_ADDR 0x400D4000 #define NPCX_TWD_BASE_ADDR 0x400D8000 /* Multi-Modules Map */ #define NPCX_PWM_BASE_ADDR(mdl) (0x40080000 + ((mdl) * 0x2000L)) #define NPCX_GPIO_BASE_ADDR(mdl) (0x40081000 + ((mdl) * 0x2000L)) #define NPCX_ITIM_BASE_ADDR(mdl) (0x400B0000 + ((mdl) * 0x2000L)) #define NPCX_MIWU_BASE_ADDR(mdl) (0x400BB000 + ((mdl) * 0x2000L)) #define NPCX_MFT_BASE_ADDR(mdl) (0x400E1000 + ((mdl) * 0x2000L)) #define NPCX_PM_CH_BASE_ADDR(mdl) (0x400C9000 + ((mdl) * 0x2000L)) /* * NPCX-IRQ numbers */ #define NPCX_IRQ_0 0 #define NPCX_IRQ_1 1 #define NPCX_IRQ_2 2 #define NPCX_IRQ_3 3 #define NPCX_IRQ_4 4 #define NPCX_IRQ_5 5 #define NPCX_IRQ_6 6 #define NPCX_IRQ_7 7 #define NPCX_IRQ_8 8 #define NPCX_IRQ_9 9 #define NPCX_IRQ_10 10 #define NPCX_IRQ_11 11 #define NPCX_IRQ_12 12 #define NPCX_IRQ_13 13 #define NPCX_IRQ_14 14 #define NPCX_IRQ_15 15 #define NPCX_IRQ_16 16 #define NPCX_IRQ_17 17 #define NPCX_IRQ_18 18 #define NPCX_IRQ_19 19 #define NPCX_IRQ_20 20 #define NPCX_IRQ_21 21 #define NPCX_IRQ_22 22 #define NPCX_IRQ_23 23 #define NPCX_IRQ_24 24 #define NPCX_IRQ_25 25 #define NPCX_IRQ_26 26 #define NPCX_IRQ_27 27 #define NPCX_IRQ_28 28 #define NPCX_IRQ_29 29 #define NPCX_IRQ_30 30 #define NPCX_IRQ_31 31 #define NPCX_IRQ_32 32 #define NPCX_IRQ_33 33 #define NPCX_IRQ_34 34 #define NPCX_IRQ_35 35 #define NPCX_IRQ_36 36 #define NPCX_IRQ_37 37 #define NPCX_IRQ_38 38 #define NPCX_IRQ_39 39 #define NPCX_IRQ_40 40 #define NPCX_IRQ_41 41 #define NPCX_IRQ_42 42 #define NPCX_IRQ_43 43 #define NPCX_IRQ_44 44 #define NPCX_IRQ_45 45 #define NPCX_IRQ_46 46 #define NPCX_IRQ_47 47 #define NPCX_IRQ_48 48 #define NPCX_IRQ_49 49 #define NPCX_IRQ_50 50 #define NPCX_IRQ_51 51 #define NPCX_IRQ_52 52 #define NPCX_IRQ_53 53 #define NPCX_IRQ_54 54 #define NPCX_IRQ_55 55 #define NPCX_IRQ_56 56 #define NPCX_IRQ_57 57 #define NPCX_IRQ_58 58 #define NPCX_IRQ_59 59 #define NPCX_IRQ_60 60 #define NPCX_IRQ_61 61 #define NPCX_IRQ_62 62 #define NPCX_IRQ_63 63 #define NPCX_IRQ_COUNT 64 /******************************************************************************/ /* High Frequency Clock Generator (HFCG) registers */ #define NPCX_HFCGCTRL REG8(NPCX_HFCG_BASE_ADDR + 0x000) #define NPCX_HFCGML REG8(NPCX_HFCG_BASE_ADDR + 0x002) #define NPCX_HFCGMH REG8(NPCX_HFCG_BASE_ADDR + 0x004) #define NPCX_HFCGN REG8(NPCX_HFCG_BASE_ADDR + 0x006) #define NPCX_HFCGP REG8(NPCX_HFCG_BASE_ADDR + 0x008) #define NPCX_HFCBCD REG8(NPCX_HFCG_BASE_ADDR + 0x010) /* HFCG register fields */ #define NPCX_HFCGCTRL_LOAD 0 #define NPCX_HFCGCTRL_LOCK 2 #define NPCX_HFCGCTRL_CLK_CHNG 7 /******************************************************************************/ /* Low Frequency Clock Generator (LFCG) registers */ #define NPCX_LFCGCTL REG8(NPCX_LFCG_BASE_ADDR + 0x000) #define NPCX_HFRDI REG16(NPCX_LFCG_BASE_ADDR + 0x002) #define NPCX_HFRDF REG16(NPCX_LFCG_BASE_ADDR + 0x004) #define NPCX_FRCDIV REG16(NPCX_LFCG_BASE_ADDR + 0x006) #define NPCX_DIVCOR1 REG16(NPCX_LFCG_BASE_ADDR + 0x008) #define NPCX_DIVCOR2 REG16(NPCX_LFCG_BASE_ADDR + 0x00A) #define NPCX_LFCGCTL2 REG8(NPCX_LFCG_BASE_ADDR + 0x014) /* LFCG register fields */ #define NPCX_LFCGCTL_XTCLK_VAL 7 #define NPCX_LFCGCTL2_XT_OSC_SL_EN 6 /******************************************************************************/ /* CR UART Register */ #define NPCX_UTBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x000) #define NPCX_URBUF(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x002) #define NPCX_UICTRL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x004) #define NPCX_USTAT(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x006) #define NPCX_UFRS(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x008) #define NPCX_UMDSL(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00A) #define NPCX_UBAUD(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00C) #define NPCX_UPSR(n) REG8(NPCX_CR_UART_BASE_ADDR(n) + 0x00E) /******************************************************************************/ /* KBSCAN registers */ #define NPCX_KBSIN REG8(NPCX_KBSCAN_REGS_BASE + 0x04) #define NPCX_KBSINPU REG8(NPCX_KBSCAN_REGS_BASE + 0x05) #define NPCX_KBSOUT0 REG16(NPCX_KBSCAN_REGS_BASE + 0x06) #define NPCX_KBSOUT1 REG16(NPCX_KBSCAN_REGS_BASE + 0x08) #define NPCX_KBS_BUF_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0A) #define NPCX_KBS_BUF_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0B) #define NPCX_KBSEVT REG8(NPCX_KBSCAN_REGS_BASE + 0x0C) #define NPCX_KBSCTL REG8(NPCX_KBSCAN_REGS_BASE + 0x0D) #define NPCX_KBS_CFG_INDX REG8(NPCX_KBSCAN_REGS_BASE + 0x0E) #define NPCX_KBS_CFG_DATA REG8(NPCX_KBSCAN_REGS_BASE + 0x0F) /* KBSCAN register fields */ #define NPCX_KBSBUFINDX 0 #define NPCX_KBSDONE 0 #define NPCX_KBSERR 1 #define NPCX_KBSSTART 0 #define NPCX_KBSMODE 1 #define NPCX_KBSIEN 2 #define NPCX_KBSINC 3 #define NPCX_KBSCFGINDX 0 /* KBSCAN definitions */ #define KB_ROW_NUM 8 /* Rows numbers of keyboard matrix */ #define KB_COL_NUM 18 /* Columns numbers of keyboard matrix */ #define KB_ROW_MASK ((1<= 0 && i <= 1) ? ESPI_VW_TYPE_INT_EV : \ (i >= 2 && i <= 7) ? ESPI_VW_TYPE_SYS_EV : \ (i >= 64 && i <= 127) ? ESPI_VW_TYPE_PLT : \ (i >= 128 && i <= 255) ? ESPI_VW_TYPE_GPIO : \ ESPI_VW_TYPE_NONE) /* Bit field manipulation for VWEVMS Value */ #define VWEVMS_INX(i) ((i<<8) & 0x00007F00) #define VWEVMS_INX_EN(n) ((n<<15) & 0x00008000) #define VWEVMS_PLTRST_EN(p) ((p<<17) & 0x00020000) #define VWEVMS_INT_EN(e) ((e<<18) & 0x00040000) #define VWEVMS_ESPIRST_EN(r) ((r<<19) & 0x00080000) #define VWEVMS_FIELD(i, n, p, e, r) (VWEVMS_INX(i) | VWEVMS_INX_EN(n) | \ VWEVMS_PLTRST_EN(p) | VWEVMS_INTWK_EN(e) | \ VWEVMS_ESPIRST_EN(r)) #define VWEVMS_IDX_GET(reg) (((reg & 0x00007F00)>>8)) /* Bit field manipulation for VWEVSM Value */ #define VWEVSM_VALID_N(v) ((v<<4) & 0x000000F0) #define VWEVSM_INX(i) ((i<<8) & 0x00007F00) #define VWEVSM_INX_EN(n) ((n<<15) & 0x00008000) #define VWEVSM_DIRTY(d) ((d<<16) & 0x00010000) #define VWEVSM_PLTRST_EN(p) ((p<<17) & 0x00020000) #define VWEVSM_CDRST_EN(c) ((c<<19) & 0x00080000) #define VWEVSM_FIELD(i, n, v, p, c) (VWEVSM_INX(i) | VWEVSM_INX_EN(n) | \ VWEVSM_VALID_N(v) | VWEVSM_PLTRST_EN(p) |\ VWEVSM_CDRST_EN(c)) #define VWEVSM_IDX_GET(reg) (((reg & 0x00007F00)>>8)) /* define macro to handle SMI/SCI Virtual Wire */ /* Read SMI VWire status from VWEVSM(offset 2) register. */ #define SMI_STATUS_MASK ((uint8_t) (NPCX_VWEVSM(2) & 0x00000002)) /* * Read SCI VWire status from VWEVSM(offset 2) register. * Left shift 2 to meet the SCIB field in HIPMIC register. */ #define SCI_STATUS_MASK (((uint8_t) (NPCX_VWEVSM(2) & 0x00000001)) << 2) #define SCIB_MASK(v) (v << NPCX_HIPMIC_SCIB) #define SMIB_MASK(v) (v << NPCX_HIPMIC_SMIB) #define NPCX_VW_SCI(level) ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \ SMI_STATUS_MASK | SCIB_MASK(level)) #define NPCX_VW_SMI(level) ((NPCX_HIPMIC(PM_CHAN_1) & 0xF9) | \ SCI_STATUS_MASK | SMIB_MASK(level)) /* eSPI enumeration */ /* eSPI channels */ enum { NPCX_ESPI_CH_PC = 0, NPCX_ESPI_CH_VW, NPCX_ESPI_CH_OOB, NPCX_ESPI_CH_FLASH, NPCX_ESPI_CH_COUNT, NPCX_ESPI_CH_GENERIC, NPCX_ESPI_CH_NONE = 0xFF }; /* eSPI IO modes */ enum { NPCX_ESPI_IO_MODE_SINGLE = 0, NPCX_ESPI_IO_MODE_DUAL = 1, NPCX_ESPI_IO_MODE_QUAD = 2, NPCX_ESPI_IO_MODE_ALL = 3, NPCX_ESPI_IO_MODE_NONE = 0xFF }; /* eSPI IO mode selected */ enum { NPCX_ESPI_IO_MODE_SEL_SINGLE = 0, NPCX_ESPI_IO_MODE_SEL_DUAL = 1, NPCX_ESPI_IO_MODE_SEL_QUARD = 2, NPCX_ESPI_IO_MODE_SEL_NONE = 0xFF }; /* VW types */ enum { ESPI_VW_TYPE_INT_EV, /* Interrupt event */ ESPI_VW_TYPE_SYS_EV, /* System Event */ ESPI_VW_TYPE_PLT, /* Platform specific */ ESPI_VW_TYPE_GPIO, /* General Purpose I/O Expander */ ESPI_VW_TYPE_NUM, ESPI_VW_TYPE_NONE = 0xFF }; /******************************************************************************/ /* GDMA (General DMA) Registers */ #define NPCX_GDMA_CTL REG32(NPCX_GDMA_BASE_ADDR + 0x000) #define NPCX_GDMA_SRCB REG32(NPCX_GDMA_BASE_ADDR + 0x004) #define NPCX_GDMA_DSTB REG32(NPCX_GDMA_BASE_ADDR + 0x008) #define NPCX_GDMA_TCNT REG32(NPCX_GDMA_BASE_ADDR + 0x00C) #define NPCX_GDMA_CSRC REG32(NPCX_GDMA_BASE_ADDR + 0x010) #define NPCX_GDMA_CDST REG32(NPCX_GDMA_BASE_ADDR + 0x014) #define NPCX_GDMA_CTCNT REG32(NPCX_GDMA_BASE_ADDR + 0x018) /******************************************************************************/ /* GDMA register fields */ #define NPCX_GDMA_CTL_GDMAEN 0 #define NPCX_GDMA_CTL_GDMAMS FIELD(2, 2) #define NPCX_GDMA_CTL_DADIR 4 #define NPCX_GDMA_CTL_SADIR 5 #define NPCX_GDMA_CTL_SAFIX 7 #define NPCX_GDMA_CTL_SIEN 8 #define NPCX_GDMA_CTL_BME 9 #define NPCX_GDMA_CTL_SBMS 11 #define NPCX_GDMA_CTL_TWS FIELD(12, 2) #define NPCX_GDMA_CTL_DM 15 #define NPCX_GDMA_CTL_SOFTREQ 16 #define NPCX_GDMA_CTL_TC 18 #define NPCX_GDMA_CTL_GDMAERR 20 #define NPCX_GDMA_CTL_BLOCK_BUG_CORRECTION_DISABLE 26 /******************************************************************************/ /* Nuvoton internal used only registers */ #define NPCX_INTERNAL_CTRL1 REG8(0x400DB000) #define NPCX_INTERNAL_CTRL2 REG8(0x400DD000) #define NPCX_INTERNAL_CTRL3 REG8(0x400DF000) /******************************************************************************/ /* Optional M4 Registers */ #define CPU_DHCSR REG32(0xE000EDF0) #define CPU_MPU_CTRL REG32(0xE000ED94) #define CPU_MPU_RNR REG32(0xE000ED98) #define CPU_MPU_RBAR REG32(0xE000ED9C) #define CPU_MPU_RASR REG32(0xE000EDA0) /******************************************************************************/ /* Flash Utiltiy definition */ /* * Flash commands for the W25Q16CV SPI flash */ #define CMD_READ_ID 0x9F #define CMD_READ_MAN_DEV_ID 0x90 #define CMD_WRITE_EN 0x06 #define CMD_WRITE_STATUS 0x50 #define CMD_READ_STATUS_REG 0x05 #define CMD_READ_STATUS_REG2 0x35 #define CMD_WRITE_STATUS_REG 0x01 #define CMD_FLASH_PROGRAM 0x02 #define CMD_SECTOR_ERASE 0x20 #define CMD_BLOCK_32K_ERASE 0x52 #define CMD_BLOCK_64K_ERASE 0xd8 #define CMD_PROGRAM_UINT_SIZE 0x08 #define CMD_PAGE_SIZE 0x00 #define CMD_READ_ID_TYPE 0x47 #define CMD_FAST_READ 0x0B /* * Status registers for the W25Q16CV SPI flash */ #define SPI_FLASH_SR2_SUS BIT(7) #define SPI_FLASH_SR2_CMP BIT(6) #define SPI_FLASH_SR2_LB3 BIT(5) #define SPI_FLASH_SR2_LB2 BIT(4) #define SPI_FLASH_SR2_LB1 BIT(3) #define SPI_FLASH_SR2_QE BIT(1) #define SPI_FLASH_SR2_SRP1 BIT(0) #define SPI_FLASH_SR1_SRP0 BIT(7) #define SPI_FLASH_SR1_SEC BIT(6) #define SPI_FLASH_SR1_TB BIT(5) #define SPI_FLASH_SR1_BP2 BIT(4) #define SPI_FLASH_SR1_BP1 BIT(3) #define SPI_FLASH_SR1_BP0 BIT(2) #define SPI_FLASH_SR1_WEL BIT(1) #define SPI_FLASH_SR1_BUSY BIT(0) /* 0: F_CS0 1: F_CS1_1(GPIO86) 2:F_CS1_2(GPIOA6) */ #define FIU_CHIP_SELECT 0 /* Create UMA control mask */ #define MASK(bit) (0x1 << (bit)) #define A_SIZE 0x03 /* 0: No ADR field 1: 3-bytes ADR field */ #define C_SIZE 0x04 /* 0: 1-Byte CMD field 1:No CMD field */ #define RD_WR 0x05 /* 0: Read 1: Write */ #define DEV_NUM 0x06 /* 0: PVT is used 1: SHD is used */ #define EXEC_DONE 0x07 #define D_SIZE_1 0x01 #define D_SIZE_2 0x02 #define D_SIZE_3 0x03 #define D_SIZE_4 0x04 #define FLASH_SEL MASK(DEV_NUM) #define MASK_CMD_ONLY (MASK(EXEC_DONE) | FLASH_SEL) #define MASK_CMD_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(A_SIZE)) #define MASK_CMD_ADR_WR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ |MASK(A_SIZE) | D_SIZE_1) #define MASK_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_1) #define MASK_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_2) #define MASK_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_3) #define MASK_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(C_SIZE) | D_SIZE_4) #define MASK_CMD_RD_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_1) #define MASK_CMD_RD_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_2) #define MASK_CMD_RD_3BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_3) #define MASK_CMD_RD_4BYTE (MASK(EXEC_DONE) | FLASH_SEL | D_SIZE_4) #define MASK_CMD_WR_ONLY (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR)) #define MASK_CMD_WR_1BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ | MASK(C_SIZE) | D_SIZE_1) #define MASK_CMD_WR_2BYTE (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ | MASK(C_SIZE) | D_SIZE_2) #define MASK_CMD_WR_ADR (MASK(EXEC_DONE) | FLASH_SEL | MASK(RD_WR) \ | MASK(A_SIZE)) /******************************************************************************/ /* APM (Audio Processing Module) Registers */ #define NPCX_APM_SR REG8(NPCX_APM_BASE_ADDR + 0x000) #define NPCX_APM_SR2 REG8(NPCX_APM_BASE_ADDR + 0x004) #define NPCX_APM_ICR REG8(NPCX_APM_BASE_ADDR + 0x008) #define NPCX_APM_IMR REG8(NPCX_APM_BASE_ADDR + 0x00C) #define NPCX_APM_IFR REG8(NPCX_APM_BASE_ADDR + 0x010) #define NPCX_APM_CR_APM REG8(NPCX_APM_BASE_ADDR + 0x014) #define NPCX_APM_CR_CK REG8(NPCX_APM_BASE_ADDR + 0x018) #define NPCX_APM_AICR_ADC REG8(NPCX_APM_BASE_ADDR + 0x01C) #define NPCX_APM_FCR_ADC REG8(NPCX_APM_BASE_ADDR + 0x020) #define NPCX_APM_CR_DMIC REG8(NPCX_APM_BASE_ADDR + 0x02C) #define NPCX_APM_CR_ADC REG8(NPCX_APM_BASE_ADDR + 0x030) #define NPCX_APM_CR_MIX REG8(NPCX_APM_BASE_ADDR + 0x034) #define NPCX_APM_DR_MIX REG8(NPCX_APM_BASE_ADDR + 0x038) #define NPCX_APM_GCR_ADCL REG8(NPCX_APM_BASE_ADDR + 0x03C) #define NPCX_APM_GCR_ADCR REG8(NPCX_APM_BASE_ADDR + 0x040) #define NPCX_APM_GCR_MIXADCL REG8(NPCX_APM_BASE_ADDR + 0x044) #define NPCX_APM_GCR_MIXADCR REG8(NPCX_APM_BASE_ADDR + 0x048) #define NPCX_APM_CR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x04C) #define NPCX_APM_DR_ADC_AGC REG8(NPCX_APM_BASE_ADDR + 0x050) #define NPCX_APM_SR_ADC_AGCDGL REG8(NPCX_APM_BASE_ADDR + 0x054) #define NPCX_APM_SR_ADC_AGCDGR REG8(NPCX_APM_BASE_ADDR + 0x058) #define NPCX_APM_CR_VAD REG8(NPCX_APM_BASE_ADDR + 0x05C) #define NPCX_APM_DR_VAD REG8(NPCX_APM_BASE_ADDR + 0x060) #define NPCX_APM_CR_VAD_CMD REG8(NPCX_APM_BASE_ADDR + 0x064) #define NPCX_APM_CR_TR REG8(NPCX_APM_BASE_ADDR + 0x068) #define NPCX_APM_DR_TR REG8(NPCX_APM_BASE_ADDR + 0x06C) #define NPCX_APM_SR_TR1 REG8(NPCX_APM_BASE_ADDR + 0x070) #define NPCX_APM_SR_TR_SRCADC REG8(NPCX_APM_BASE_ADDR + 0x074) /******************************************************************************/ /* APM register fields */ #define NPCX_APM_SR_IRQ_PEND 6 #define NPCX_APM_SR2_SMUTEIP 6 #define NPCX_APM_ICR_INTR_MODE FIELD(6, 2) #define NPCX_APM_IMR_VAD_DTC_MASK 6 #define NPCX_APM_IFR_VAD_DTC 6 #define NPCX_APM_CR_APM_PD 0 #define NPCX_APM_CR_APM_AGC_DIS FIELD(1, 2) #define NPCX_APM_CR_CK_MCLK_FREQ FIELD(0, 2) #define NPCX_APM_AICR_ADC_ADC_AUDIOIF FIELD(0, 2) #define NPCX_APM_AICR_ADC_PD_AICR_ADC 4 #define NPCX_APM_AICR_ADC_ADC_ADWL FIELD(6, 2) #define NPCX_APM_FCR_ADC_ADC_FREQ FIELD(0, 4) #define NPCX_APM_FCR_ADC_ADC_WNF FIELD(4, 2) #define NPCX_APM_FCR_ADC_ADC_HPF 6 #define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_RIGHT FIELD(0, 2) #define NPCX_APM_CR_DMIC_ADC_DMIC_SEL_LEFT FIELD(2, 2) #define NPCX_APM_CR_DMIC_ADC_DMIC_RATE FIELD(4, 3) #define NPCX_APM_CR_DMIC_PD_DMIC 7 #define NPCX_APM_CR_ADC_ADC_SOFT_MUTE 7 #define NPCX_APM_CR_MIX_MIX_ADD FIELD(0, 6) #define NPCX_APM_CR_MIX_MIX_LOAD 6 #define NPCX_APM_DR_MIX_MIX_DATA FIELD(0, 8) #define NPCX_APM_MIX_2_AIADCR_SEL FIELD(4, 2) #define NPCX_APM_MIX_2_AIADCL_SEL FIELD(6, 2) #define NPCX_APM_GCR_ADCL_GIDL FIELD(0, 6) #define NPCX_APM_GCR_ADCL_LRGID 7 #define NPCX_APM_GCR_ADCR_GIDR FIELD(0, 6) #define NPCX_APM_GCR_MIXADCL_GIMIXL FIELD(0, 6) #define NPCX_APM_GCR_MIXADCR_GIMIXR FIELD(0, 6) #define NPCX_APM_CR_ADC_AGC_ADC_AGC_ADD FIELD(0, 6) #define NPCX_APM_CR_ADC_AGC_ADC_AGC_LOAD 6 #define NPCX_APM_CR_ADC_AGC_ADC_AGC_EN 7 #define NPCX_APM_DR_ADC_AGC_ADC_AGC_DATA FIELD(0, 8) #define NPCX_ADC_AGC_0_AGC_TARGET FIELD(2, 4) #define NPCX_ADC_AGC_0_AGC_STEREO 6 #define NPCX_ADC_AGC_1_HOLD FIELD(0, 4) #define NPCX_ADC_AGC_1_NG_THR FIELD(4, 3) #define NPCX_ADC_AGC_1_NG_EN 7 #define NPCX_ADC_AGC_2_DCY FIELD(0, 4) #define NPCX_ADC_AGC_2_ATK FIELD(4, 4) #define NPCX_ADC_AGC_3_AGC_MAX FIELD(0, 5) #define NPCX_ADC_AGC_4_AGC_MIN FIELD(0, 5) #define NPCX_APM_CR_VAD_VAD_ADD FIELD(0, 6) #define NPCX_APM_CR_VAD_VAD_LOAD 6 #define NPCX_APM_CR_VAD_VAD_EN 7 #define NPCX_APM_DR_VAD_VAD_DATA FIELD(0, 8) #define NPCX_APM_CR_VAD_CMD_VAD_RESTART 0 #define NPCX_APM_CR_TR_FAST_ON 7 #define NPCX_VAD_0_VAD_INSEL FIELD(0, 2) #define NPCX_VAD_0_VAD_DMIC_FREQ FIELD(2, 3) #define NPCX_VAD_0_VAD_ADC_WAKEUP 5 #define NPCX_VAD_0_ZCD_EN 6 #define NPCX_VAD_1_VAD_POWER_SENS FIELD(0, 5) #define NPCX_APM_CONTROL_ADD FIELD(0, 6) #define NPCX_APM_CONTROL_LOAD 6 /******************************************************************************/ /* FMUL2 (Frequency Multiplier Module 2) Registers */ #define NPCX_FMUL2_FM2CTRL REG8(NPCX_FMUL2_BASE_ADDR + 0x000) #define NPCX_FMUL2_FM2ML REG8(NPCX_FMUL2_BASE_ADDR + 0x002) #define NPCX_FMUL2_FM2MH REG8(NPCX_FMUL2_BASE_ADDR + 0x004) #define NPCX_FMUL2_FM2N REG8(NPCX_FMUL2_BASE_ADDR + 0x006) #define NPCX_FMUL2_FM2P REG8(NPCX_FMUL2_BASE_ADDR + 0x008) #define NPCX_FMUL2_FM2_VER REG8(NPCX_FMUL2_BASE_ADDR + 0x00A) /******************************************************************************/ /* FMUL2 register fields */ #define NPCX_FMUL2_FM2CTRL_LOAD2 0 #define NPCX_FMUL2_FM2CTRL_LOCK2 2 #define NPCX_FMUL2_FM2CTRL_FMUL2_DIS 5 #define NPCX_FMUL2_FM2CTRL_TUNE_DIS 6 #define NPCX_FMUL2_FM2CTRL_CLK2_CHNG 7 #define NPCX_FMUL2_FM2N_FM2N FIELD(0, 6) #define NPCX_FMUL2_FM2P_WFPRED FIELD(4, 4) /******************************************************************************/ /* WOV (Wake-on-Voice) Registers */ #define NPCX_WOV_CLOCK_CNTL REG32(NPCX_WOV_BASE_ADDR + 0x000) #define NPCX_WOV_PLL_CNTL1 REG32(NPCX_WOV_BASE_ADDR + 0x004) #define NPCX_WOV_PLL_CNTL2 REG32(NPCX_WOV_BASE_ADDR + 0x008) #define NPCX_WOV_FIFO_CNT REG32(NPCX_WOV_BASE_ADDR + 0x00C) #define NPCX_WOV_FIFO_OUT REG32(NPCX_WOV_BASE_ADDR + 0x010) #define NPCX_WOV_STATUS REG32(NPCX_WOV_BASE_ADDR + 0x014) #define NPCX_WOV_WOV_INTEN REG32(NPCX_WOV_BASE_ADDR + 0x018) #define NPCX_WOV_APM_CTRL REG32(NPCX_WOV_BASE_ADDR + 0x01C) #define NPCX_WOV_I2S_CNTL(n) REG32(NPCX_WOV_BASE_ADDR + 0x020 + (4*n)) #define NPCX_WOV_VERSION REG32(NPCX_WOV_BASE_ADDR + 0x030) /******************************************************************************/ /* WOV register fields */ #define NPCX_WOV_CLOCK_CNT_CLK_SEL 0 #define NPCX_WOV_CLOCK_CNT_DMIC_EN 3 #define NPCX_WOV_CLOCK_CNT_PLL_EDIV_SEL 7 #define NPCX_WOV_CLOCK_CNT_PLL_EDIV FIELD(8, 7) #define NPCX_WOV_CLOCK_CNT_PLL_EDIV_DC FIELD(16, 7) #define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_EN 24 #define NPCX_WOV_CLOCK_CNT_DMIC_CKDIV_SEL 25 #define NPCX_WOV_FIFO_CNT_FIFO_ITHRSH FIELD(0, 6) #define NPCX_WOV_FIFO_CNT_FIFO_WTHRSH FIELD(6, 6) #define NPCX_WOV_FIFO_CNT_I2S_FFRST 13 #define NPCX_WOV_FIFO_CNT_CORE_FFRST 14 #define NPCX_WOV_FIFO_CNT_CFIFO_ISEL FIELD(16, 3) #define NPCX_WOV_STATUS_CFIFO_CNT FIELD(0, 8) #define NPCX_WOV_STATUS_CFIFO_NE 8 #define NPCX_WOV_STATUS_CFIFO_OIT 9 #define NPCX_WOV_STATUS_CFIFO_OWT 10 #define NPCX_WOV_STATUS_CFIFO_OVRN 11 #define NPCX_WOV_STATUS_I2S_FIFO_OVRN 12 #define NPCX_WOV_STATUS_I2S_FIFO_UNDRN 13 #define NPCX_WOV_STATUS_BITS FIELD(9, 6) #define NPCX_WOV_INTEN_VAD_INTEN 0 #define NPCX_WOV_INTEN_VAD_WKEN 1 #define NPCX_WOV_INTEN_CFIFO_NE_IE 8 #define NPCX_WOV_INTEN_CFIFO_OIT_IE 9 #define NPCX_WOV_INTEN_CFIFO_OWT_WE 10 #define NPCX_WOV_INTEN_CFIFO_OVRN_IE 11 #define NPCX_WOV_INTEN_I2S_FIFO_OVRN_IE 12 #define NPCX_WOV_INTEN_I2S_FIFO_UNDRN_IE 13 #define NPCX_WOV_APM_CTRL_APM_RST 0 #define NPCX_WOV_PLL_CNTL1_PLL_PWDEN 0 #define NPCX_WOV_PLL_CNTL1_PLL_OTDV1 FIELD(4, 4) #define NPCX_WOV_PLL_CNTL1_PLL_OTDV2 FIELD(8, 4) #define NPCX_WOV_PLL_CNTL1_PLL_LOCKI 15 #define NPCX_WOV_PLL_CNTL2_PLL_FBDV FIELD(0, 12) #define NPCX_WOV_PLL_CNTL2_PLL_INDV FIELD(12, 4) #define NPCX_WOV_I2S_CNTL_I2S_BCNT FIELD(0, 5) #define NPCX_WOV_I2S_CNTL_I2S_TRIG 5 #define NPCX_WOV_I2S_CNTL_I2S_LBHIZ 6 #define NPCX_WOV_I2S_CNTL_I2S_ST_DEL FIELD(7, 9) #define NPCX_WOV_I2S_CNTL_I2S_CHAN FIELD(0, 16) #define NPCX_WOV_I2S_CNTL0_I2S_HIZD 16 #define NPCX_WOV_I2S_CNTL0_I2S_HIZ 17 #define NPCX_WOV_I2S_CNTL0_I2S_SCLK_INV 18 #define NPCX_WOV_I2S_CNTL0_I2S_OPS 19 #define NPCX_WOV_I2S_CNTL0_I2S_OPE 20 #define NPCX_WOV_I2S_CNTL0_I2S_IPS 21 #define NPCX_WOV_I2S_CNTL0_I2S_IPE 22 #define NPCX_WOV_I2S_CNTL0_I2S_TST 23 #define NPCX_WOV_I2S_CNTL1_I2S_CHN1_DIS 24 /******************************************************************************/ /* PS/2 registers */ #define NPCX_PS2_PSDAT REG8(NPCX_PS2_BASE_ADDR + 0x000) #define NPCX_PS2_PSTAT REG8(NPCX_PS2_BASE_ADDR + 0x002) #define NPCX_PS2_PSCON REG8(NPCX_PS2_BASE_ADDR + 0x004) #define NPCX_PS2_PSOSIG REG8(NPCX_PS2_BASE_ADDR + 0x006) #define NPCX_PS2_PSISIG REG8(NPCX_PS2_BASE_ADDR + 0x008) #define NPCX_PS2_PSIEN REG8(NPCX_PS2_BASE_ADDR + 0x00A) /* PS/2 register field */ #define NPCX_PS2_PSTAT_SOT 0 #define NPCX_PS2_PSTAT_EOT 1 #define NPCX_PS2_PSTAT_PERR 2 #define NPCX_PS2_PSTAT_ACH FIELD(3, 3) #define NPCX_PS2_PSTAT_RFERR 6 #define NPCX_PS2_PSCON_EN 0 #define NPCX_PS2_PSCON_XMT 1 #define NPCX_PS2_PSCON_HDRV FIELD(2, 2) #define NPCX_PS2_PSCON_IDB FIELD(4, 3) #define NPCX_PS2_PSCON_WPUED 7 #define NPCX_PS2_PSOSIG_WDAT0 0 #define NPCX_PS2_PSOSIG_WDAT1 1 #define NPCX_PS2_PSOSIG_WDAT2 2 #define NPCX_PS2_PSOSIG_CLK0 3 #define NPCX_PS2_PSOSIG_CLK1 4 #define NPCX_PS2_PSOSIG_CLK2 5 #define NPCX_PS2_PSOSIG_WDAT3 6 #define NPCX_PS2_PSOSIG_CLK3 7 #define NPCX_PS2_PSOSIG_CLK(n) (((n) < NPCX_PS2_CH3) ? \ ((n) + 3) : 7) #define NPCX_PS2_PSOSIG_WDAT(n) (((n) < NPCX_PS2_CH3) ? \ ((n) + 0) : 6) #define NPCX_PS2_PSOSIG_CLK_MASK_ALL \ (BIT(NPCX_PS2_PSOSIG_CLK0) | \ BIT(NPCX_PS2_PSOSIG_CLK1) | \ BIT(NPCX_PS2_PSOSIG_CLK2) | \ BIT(NPCX_PS2_PSOSIG_CLK3)) #define NPCX_PS2_PSISIG_RDAT0 0 #define NPCX_PS2_PSISIG_RDAT1 1 #define NPCX_PS2_PSISIG_RDAT2 2 #define NPCX_PS2_PSISIG_RCLK0 3 #define NPCX_PS2_PSISIG_RCLK1 4 #define NPCX_PS2_PSISIG_RCLK2 5 #define NPCX_PS2_PSISIG_RDAT3 6 #define NPCX_PS2_PSISIG_RCLK3 7 #define NPCX_PS2_PSIEN_SOTIE 0 #define NPCX_PS2_PSIEN_EOTIE 1 #define NPCX_PS2_PSIEN_PS2_WUE 4 #define NPCX_PS2_PSIEN_PS2_CLK_SEL 7 #ifndef CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC extern const enum gpio_signal hibernate_wake_pins[]; extern const int hibernate_wake_pins_used; #else extern enum gpio_signal hibernate_wake_pins[]; extern int hibernate_wake_pins_used; #endif #ifndef NPCX_UART_MODULE2 #define NPCX_UART_MODULE2 0 #endif /* NPCX_UART_MODULE2 */ #if defined(CHIP_FAMILY_NPCX5) #include "registers-npcx5.h" #elif defined(CHIP_FAMILY_NPCX7) #include "registers-npcx7.h" #elif defined(CHIP_FAMILY_NPCX9) #include "registers-npcx9.h" #else #error "Unsupported chip family" #endif #endif /* __CROS_EC_REGISTERS_H */