# Copyright 2021 The ChromiumOS Authors
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.

if PLATFORM_EC_HOST_INTERFACE_ESPI

config PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S3
	bool "SLP_S3 is an eSPI virtual wire instead of a GPIO"
	help
	  For power sequencing, use an eSPI virtual wire instead of
	  defining GPIO_PCH_SLP_S3 in the GPIO device tree.

config PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S4
	bool "SLP_S4 is an eSPI virtual wire instead of a GPIO"
	help
	  For power sequencing, use an eSPI virtual wire instead of
	  defining GPIO_PCH_SLP_S4 in the GPIO device tree.

config PLATFORM_EC_HOST_INTERFACE_ESPI_VW_SLP_S5
	bool "SLP_S5 is an eSPI virtual wire instead of an alias for SLP_S4"
	help
	  For power sequencing, use an eSPI virtual wire to read the SLP_S5 line,
	  as opposed to merging it into the same net as SLP_S4.

config PLATFORM_EC_HOST_INTERFACE_ESPI_RESET_SLP_SX_VW_ON_ESPI_RST
	bool "Reset SLP VW signals on eSPI reset"
	help
	  Enable this config to reset SLP* VW when eSPI_RST is asserted
	  for the Global Reset event case.  Don't enable this config if
	  the platform implements the Deep-Sx entry as EC needs to
	  maintain these pins' states per request. Note that this is
	  currently unimplemented for Zephyr. Please see b/183148073.

config PLATFORM_EC_HOST_INTERFACE_ESPI_DEFAULT_VW_WIDTH_US
	int "Virtual wire pulse width (microseconds)"
	default 65
	help
	  The minimum pulse width of a eSPI/LPC virtual wire signals to the
	  host. May vary by host chipset.

endif # PLATFORM_EC_HOST_INTERFACE_ESPI