/* Copyright 2021 The ChromiumOS Authors
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

#include <dt-bindings/gpio_defines.h>
#include <nuvoton/npcx/npcx9/npcx9-pinctrl.dtsi>

/ {
	model = "NPCX9";

	aliases {
		i2c-0 = &i2c0_0;
		i2c-1 = &i2c1_0;
		i2c-2 = &i2c2_0;
		i2c-3 = &i2c3_0;
		i2c-5 = &i2c5_0;
		i2c-7 = &i2c7_0;
	};

	chosen {
		zephyr,sram = &sram0;
		zephyr,console = &uart1;
		zephyr,shell-uart = &uart1;
		zephyr,flash = &flash0;
		zephyr,flash-controller = &int_flash;
	};

	named-i2c-ports {
		compatible = "named-i2c-ports";
	};

	named-adc-channels {
		compatible = "named-adc-channels";
	};
};

&uart1 {
	status = "okay";
	current-speed = <115200>;
	pinctrl-0 = <&uart1_2_sin_gp64 &uart1_2_sout_gp65>;
	pinctrl-names = "default";
};

&pinctrl {
	/*
	 * TODO(b/232573074): Move pinctrl to set SHI pins to GPIO mode
	 * upstream.
	 */
	 /omit-if-no-ref/ shi_gpio_gp46_47_53_55: periph-shi-gpio {
		pinmux = <&altc_shi_sl>;
		pinmux-gpio;
	};
};

/* PSL_OUT is fixed to GPIO85 in npcx9 series. */
&power_ctrl_psl {
	enable-gpios = <&gpio8 5 0>;
};