/* Copyright 2021 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ #ifndef __ZEPHYR_GPIO_MAP_H #define __ZEPHYR_GPIO_MAP_H #include #include /* Cometlake power sequencing requires this definition */ #define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(X86_PP5000_A_PGOOD) /* * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items. * * Each GPIO_INT requires three parameters: * gpio_signal - The enum gpio_signal for the interrupt gpio * interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH) * handler - The platform/ec interrupt handler. * * Ensure that this files includes all necessary headers to declare all * referenced handler functions. * * For example, one could use the follow definition: * #define EC_CROS_GPIO_INTERRUPTS \ * GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print) */ #define EC_CROS_GPIO_INTERRUPTS \ GPIO_INT(NAMED_GPIO(lid_open), GPIO_INT_EDGE_BOTH, lid_interrupt) \ GPIO_INT(NAMED_GPIO(power_button_l), GPIO_INT_EDGE_BOTH, \ power_button_interrupt) \ GPIO_INT(NAMED_GPIO(acok_od), GPIO_INT_EDGE_BOTH, extpower_interrupt) \ GPIO_INT(NAMED_GPIO(slp_s0_l), GPIO_INT_EDGE_BOTH, \ power_signal_interrupt) \ GPIO_INT(NAMED_GPIO(slp_s3_l), GPIO_INT_EDGE_BOTH, \ power_signal_interrupt) \ GPIO_INT(NAMED_GPIO(slp_s4_l), GPIO_INT_EDGE_BOTH, \ power_signal_interrupt) \ GPIO_INT(NAMED_GPIO(pg_ec_rsmrst_l), GPIO_INT_EDGE_BOTH, \ intel_x86_rsmrst_signal_interrupt) \ GPIO_INT(NAMED_GPIO(pg_ec_all_sys_pwrgd), GPIO_INT_EDGE_BOTH, \ power_signal_interrupt) \ GPIO_INT(NAMED_GPIO(pp5000_a_pg_od), GPIO_INT_EDGE_BOTH, \ power_signal_interrupt) #endif /* __ZEPHYR_GPIO_MAP_H */