/* Copyright 2022 The Chromium OS Authors. All rights reserved.
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

/ {
	chosen {
		intel-ap-pwrseq,espi = &espi0;
	};

	common-pwrseq {
		compatible = "intel,ap-pwrseq";

		sys-pwrok-delay = <10>;
		all-sys-pwrgd-timeout = <20>;
	};

	pwr-en-pp5000-s5 {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "PP5000_S5 enable output to regulator";
		enum-name = "PWR_EN_PP5000_A";
		gpios = <&gpiok 5 0>;
		output;
	};
	pwr-en-pp3300-s5 {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "PP3300_S5 enable output to LS";
		enum-name = "PWR_EN_PP3300_A";
		gpios = <&gpioc 5 0>;
		output;
	};
	pwr-pg-ec-rsmrst-odl {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "RSMRST power good from regulator";
		enum-name = "PWR_RSMRST";
		gpios = <&gpioe 1 0>;
		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
	};
	pwr-ec-pch-rsmrst-odl {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "RSMRST output to PCH";
		enum-name = "PWR_EC_PCH_RSMRST";
		gpios = <&gpioh 0 0>;
		output;
	};
	pwr-slp-s0-l {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "SLP_S0_L input from PCH";
		enum-name = "PWR_SLP_S0";
		gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
	};
	pwr-slp-s3-l {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "SLP_S3_L input from PCH";
		enum-name = "PWR_SLP_S3";
		gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
	};
	pwr-slp-sus-l {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "SLP_SUS_L input from PCH";
		enum-name = "PWR_SLP_SUS";
		gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
		interrupt-flags = <GPIO_INT_EDGE_BOTH>;
	};
	pwr-ec-soc-dsw-pwrok {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "DSW_PWROK output to PCH";
		enum-name = "PWR_EC_SOC_DSW_PWROK";
		gpios = <&gpiol 7 0>;
		output;
	};
	pwr-vccst-pwrgd-od {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "VCCST_PWRGD output to PCH";
		enum-name = "PWR_VCCST_PWRGD";
		gpios = <&gpioe 5 GPIO_OPEN_DRAIN>;
		output;
	};
	pwr-imvp9-vrrdy-od {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "VRRDY input from IMVP9";
		enum-name = "PWR_IMVP9_VRRDY";
		gpios = <&gpioj 4 0>;
	};
	pwr-pch-pwrok {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "PCH_PWROK output to PCH";
		enum-name = "PWR_PCH_PWROK";
		gpios = <&gpiod 6 GPIO_OPEN_DRAIN>;
		output;
	};
	pwr-ec-pch-sys-pwrok {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "SYS_PWROK output to PCH";
		enum-name = "PWR_EC_PCH_SYS_PWROK";
		gpios = <&gpiof 2 0>;
		output;
	};
	pwr-sys-rst-l {
		compatible = "intel,ap-pwrseq-gpio";
		dbg-label = "SYS_RESET# output to PCH";
		enum-name = "PWR_SYS_RST";
		gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
		output;
	};
	pwr-slp-s4 {
		compatible = "intel,ap-pwrseq-vw";
		dbg-label = "SLP_S4 virtual wire input from PCH";
		enum-name = "PWR_SLP_S4";
		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
		vw-invert;
	};
	pwr-slp-s5 {
		compatible = "intel,ap-pwrseq-vw";
		dbg-label = "SLP_S5 virtual wire input from PCH";
		enum-name = "PWR_SLP_S5";
		virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
		vw-invert;
	};
	pwr-all-sys-pwrgd {
		/*
		 * This is a board level signal, since this
		 * signal needs some special processing.
		 */
		compatible = "intel,ap-pwrseq-external";
		dbg-label = "Combined all power good";
		enum-name = "PWR_ALL_SYS_PWRGD";
	};
	pwr-adc-pp3300 {
		compatible = "intel,ap-pwrseq-adc";
		dbg-label = "PP3300_PROC";
		enum-name = "PWR_DSW_PWROK";
		trigger-high = <&vcmp0>;
		trigger-low = <&vcmp1>;
	};
	pwr-adc-pp1p05 {
		compatible = "intel,ap-pwrseq-adc";
		dbg-label = "PP1P05_PROC";
		enum-name = "PWR_PG_PP1P05";
		trigger-high = <&vcmp2>;
		trigger-low = <&vcmp3>;
	};

};

/*
 * Because the power signals directly reference the GPIOs,
 * the correspinding named-gpios need to have no-auto-init set.
 */
&gpio_ec_soc_dsw_pwrok {
	no-auto-init;
};
&gpio_ec_soc_pch_pwrok_od {
	no-auto-init;
};
&gpio_ec_soc_rsmrst_l {
	no-auto-init;
};
&gpio_ec_soc_sys_pwrok {
	no-auto-init;
};
&gpio_ec_soc_vccst_pwrgd_od {
	no-auto-init;
};
&gpio_en_pp3300_s5 {
	no-auto-init;
};
&gpio_en_pp5000_s5 {
	no-auto-init;
};
&gpio_imvp91_vrrdy_od {
	no-auto-init;
};
&gpio_rsmrst_pwrgd_l {
	no-auto-init;
};
&gpio_slp_s0_l {
	no-auto-init;
};
&gpio_slp_s3_l {
	no-auto-init;
};
&gpio_slp_sus_l {
	no-auto-init;
};
&gpio_sys_rst_odl {
	no-auto-init;
};
&vcmp0 {
	status = "okay";
	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
	comparison = <IT8XXX2_VCMP_GREATER>;
	/*
	 * This is 90% of nominal voltage considering voltage
	 * divider on ADC input.
	 */
	threshold-mv = <2448>;
	io-channels = <&adc0 0>;
};
&vcmp1 {
	status = "okay";
	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
	threshold-mv = <2448>;
	io-channels = <&adc0 0>;
};
&vcmp2 {
	status = "okay";
	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
	comparison = <IT8XXX2_VCMP_GREATER>;
	/* Setting at 90% of nominal voltage */
	threshold-mv = <945>;
	io-channels = <&adc0 14>;
};
&vcmp3 {
	status = "okay";
	scan-period = <IT8XXX2_VCMP_SCAN_PERIOD_600US>;
	comparison = <IT8XXX2_VCMP_LESS_OR_EQUAL>;
	threshold-mv = <945>;
	io-channels = <&adc0 14>;
};