# Copyright 2022 The ChromiumOS Authors
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.

menuconfig AP_PWRSEQ
	bool "AP Power sequencing support"
	select HAS_TASK_POWERBTN
	select GPIO_GET_CONFIG
	help
	  Enables AP power sequencing support with
	  embedded controller. This includes normal shutdown, critical
	  shutdown and reset handling.
	  Enabling this automatically enables HAS_TASK_POWERBTN since this task
	  is required to handle power button pressed/released by user.
	  Enabling this also enables retrieving the GPIO config feature
	  so that the value of output GPIOs can be determined.

if AP_PWRSEQ

module = AP_PWRSEQ
module-str = AP power sequencing
source "subsys/logging/Kconfig.template.log_config"

config AP_PWRSEQ_AUTOSTART
	bool "Start the power sequence thread automatically"
	default n
	help
	  This option starts the AP power sequence task
	  at initialisation. If not set, ap_pwrseq_thread_start()
	  needs to be called to start the task.

	  Disable this option if there is other board or module
	  initialization that must occur before the AP power sequence
	  thread is started.

config AP_PWRSEQ_STACK_SIZE
	int "AP pwrseq stack size (in bytes)"
	help
	  This option specifies the size of the stack used by the
	  AP power sequencing state machine thread handler.
	  This must be set in a board configuration. If a default
	  is set here, it cannot be overridden (if necessary), since
	  this Kconfig appears before the EC chip specific stack
	  sizes.

config AP_PWRSEQ_THREAD_PRIORITY
	int "AP pwrseq thread priority"
	default 12
	help
	  This option determines AP power sequence thread priority, this number
	  must be selected in such way thread priority is in the middle of all
	  the enabled threads.

config X86_NON_DSX_PWRSEQ
	bool
	default n
	help
	  This option enables Non Deep Sleep Well power sequencing for
	  Intel x86 chips.

config X86_NON_DSX_PWRSEQ_ADL
	bool "x86 Non Deep Sx power sequencing on ADL"
	depends on AP_X86_INTEL_ADL
	select X86_NON_DSX_PWRSEQ
	default n
	help
	  This enables AP power sequencing support for Intel Alderlake
	  family of chipset.

config X86_NON_DSX_PWRSEQ_MTL
	bool "x86 Non Deep Sx power sequencing on MTL"
	depends on AP_X86_INTEL_MTL
	select X86_NON_DSX_PWRSEQ
	default n
	help
	  This enables AP power sequencing support for Intel Meteorlake
	  family of chipset.

config X86_NON_DSX_PWRSEQ_CONSOLE
	bool "Console commands for x86 Non Deep Sx power sequencing"
	depends on X86_NON_DSX_PWRSEQ
	default n
	help
	  This option enables Non Deep Sleep Well power sequencing shell
	  console commands to debug.

config X86_NON_DSX_PWRSEQ_HOST_CMD
	bool "Host commands for x86 Non Deep Sx power sequencing"
	depends on X86_NON_DSX_PWRSEQ
	default y
	help
	  This option enables Non Deep Sleep Well power sequencing host
	  commands to debug.

config AP_PWRSEQ_HOST_SLEEP
	bool "Handle host sleep state changes"
	help
	  Enable AP power sequencing to receive and process host command
	  host sleep state changes.

config AP_PWRSEQ_S0IX
	bool "Enable power state S0ix for Intel x86 chipset"
	select AP_PWRSEQ_HOST_SLEEP
	default n
	help
	  This option enables power state S0ix for Intel x86 chipset. As
	  required, AP_PWRSEQ_HOST_SLEEP for host sleep event handling is
	  enabled.

config AP_PWRSEQ_S0IX_ERROR_RECOVERY
	bool "Detect failure to enter or exit Sleep state"
	depends on AP_PWRSEQ_HOST_SLEEP
	help
	  Enables detection of the AP failing to go to sleep, perhaps due to a
	  bug in the internal SoC periodic housekeeping code.

	  Failure information is reported via the EC_CMD_HOST_SLEEP_EVENT host
	  command.

config AP_PWRSEQ_DEBUG_MODE_COMMAND
	bool "Console commands to enable/disable AP debug mode"
	depends on X86_NON_DSX_PWRSEQ
	default y
	help
	  Intel debugger puts SOC in boot halt mode for step debugging,
	  during this time EC may lose Sx lines, This option enables console
	  command to enable debug mode and prevent force shutdown.

endif