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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* IT8380 development board configuration */
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CHIP_FAMILY_IT839X
#define CONFIG_BATTERY_SMART
#define CONFIG_FANS 1
#define CONFIG_IT83XX_KEYBOARD_KSI_WUC_INT
#define CONFIG_IT83XX_LPC_ACCESS_INT
#define CONFIG_IT83XX_PECI_WITH_INTERRUPT
#define CONFIG_IT83XX_SMCLK2_ON_GPC7
#define CONFIG_KEYBOARD_BOARD_CONFIG
#define CONFIG_KEYBOARD_PROTOCOL_8042
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_PECI_TJMAX 100
#define CONFIG_POWER_BUTTON
/* Use CS0 of SSPI */
#define CONFIG_SPI_FLASH_PORT 0
#define CONFIG_UART_HOST
/* Optional console commands */
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_SCRATCHPAD
#define CONFIG_CMD_STACKOVERFLOW
/* Debug */
#undef CONFIG_CMD_FORCETIME
#undef CONFIG_HOOK_DEBUG
#undef CONFIG_KEYBOARD_DEBUG
#undef CONFIG_UART_TX_BUF_SIZE
#define CONFIG_UART_TX_BUF_SIZE 4096
#ifndef __ASSEMBLER__
#define I2C_PORT_CHARGER 2
#define I2C_PORT_BATTERY 2
#include "gpio_signal.h"
enum pwm_channel {
PWM_CH_FAN,
PWM_CH_1,
PWM_CH_2,
PWM_CH_3,
PWM_CH_4,
PWM_CH_5,
PWM_CH_7,
/* Number of PWM channels */
PWM_CH_COUNT
};
enum adc_channel {
ADC_CH_0,
ADC_CH_1,
ADC_CH_2,
ADC_CH_3,
ADC_CH_4,
ADC_CH_5,
ADC_CH_6,
ADC_CH_7,
/* Number of ADC channels */
ADC_CH_COUNT
};
enum ec2i_setting {
EC2I_SET_KB_LDN,
EC2I_SET_KB_IRQ,
EC2I_SET_KB_ENABLE,
EC2I_SET_MOUSE_LDN,
EC2I_SET_MOUSE_IRQ,
EC2I_SET_MOUSE_ENABLE,
EC2I_SET_PMC1_LDN,
EC2I_SET_PMC1_IRQ,
EC2I_SET_PMC1_ENABLE,
EC2I_SET_PMC2_LDN,
EC2I_SET_PMC2_BASE0_MSB,
EC2I_SET_PMC2_BASE0_LSB,
EC2I_SET_PMC2_BASE1_MSB,
EC2I_SET_PMC2_BASE1_LSB,
EC2I_SET_PMC2_IRQ,
EC2I_SET_PMC2_ENABLE,
EC2I_SET_SMFI_LDN,
EC2I_SET_SMFI_H2RAM_IO_BASE,
EC2I_SET_SMFI_H2RAM_MAP_LPC_IO,
EC2I_SET_SMFI_ENABLE,
EC2I_SET_PMC3_LDN,
EC2I_SET_PMC3_BASE0_MSB,
EC2I_SET_PMC3_BASE0_LSB,
EC2I_SET_PMC3_BASE1_MSB,
EC2I_SET_PMC3_BASE1_LSB,
EC2I_SET_PMC3_IRQ,
EC2I_SET_PMC3_ENABLE,
EC2I_SET_RTCT_LDN,
EC2I_SET_RTCT_P80LB,
EC2I_SET_RTCT_P80LE,
EC2I_SET_RTCT_P80LC,
#ifdef CONFIG_UART_HOST
EC2I_SET_UART2_LDN,
EC2I_SET_UART2_IO_BASE_MSB,
EC2I_SET_UART2_IO_BASE_LSB,
EC2I_SET_UART2_IRQ,
EC2I_SET_UART2_IRQ_TYPE,
EC2I_SET_UART2_ENABLE,
#endif
/* Number of EC2I settings */
EC2I_SETTING_COUNT
};
#endif /* !__ASSEMBLER__ */
#endif /* __CROS_EC_BOARD_H */
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