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/* Copyright 2022 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "common.h"
#include "adc_chip.h"
#include "hooks.h"
#include "temp_sensor.h"
#include "thermal.h"
#include "temp_sensor/thermistor.h"
/* ADC configuration */
const struct adc_t adc_channels[] = {
[ADC_TEMP_SENSOR_1_CPU] = {
.name = "TEMP_CPU",
.input_ch = NPCX_ADC_CH0,
.factor_mul = ADC_MAX_VOLT,
.factor_div = ADC_READ_MAX + 1,
.shift = 0,
},
[ADC_TEMP_SENSOR_2_CPU_VR] = {
.name = "TEMP_CPU_VR",
.input_ch = NPCX_ADC_CH1,
.factor_mul = ADC_MAX_VOLT,
.factor_div = ADC_READ_MAX + 1,
.shift = 0,
},
[ADC_TEMP_SENSOR_3_WIFI] = {
.name = "TEMP_WIFI",
.input_ch = NPCX_ADC_CH6,
.factor_mul = ADC_MAX_VOLT,
.factor_div = ADC_READ_MAX + 1,
.shift = 0,
},
[ADC_TEMP_SENSOR_4_DIMM] = {
.name = "TEMP_DIMM",
.input_ch = NPCX_ADC_CH7,
.factor_mul = ADC_MAX_VOLT,
.factor_div = ADC_READ_MAX + 1,
.shift = 0,
},
[ADC_VBUS] = { /* 5/39 voltage divider */
.name = "VBUS",
.input_ch = NPCX_ADC_CH2,
.factor_mul = ADC_MAX_VOLT * 39,
.factor_div = (ADC_READ_MAX + 1) * 5,
},
[ADC_PWR_IN_IMON] = {
.name = "PWR_IN_IMON",
.input_ch = NPCX_ADC_CH3,
.factor_mul = ADC_MAX_VOLT,
.factor_div = ADC_READ_MAX + 1,
},
[ADC_ADP_ID] = {
.name = "ADP_ID",
.input_ch = NPCX_ADC_CH4,
.factor_mul = ADC_MAX_VOLT,
.factor_div = ADC_READ_MAX + 1,
},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* Temperature sensor configuration */
const struct temp_sensor_t temp_sensors[] = {
[TEMP_SENSOR_1_CPU] = {
.name = "CPU",
.type = TEMP_SENSOR_TYPE_BOARD,
.read = get_temp_3v3_30k9_47k_4050b,
.idx = ADC_TEMP_SENSOR_1_CPU
},
[TEMP_SENSOR_2_CPU_VR] = {
.name = "CPU VR",
.type = TEMP_SENSOR_TYPE_BOARD,
.read = get_temp_3v3_30k9_47k_4050b,
.idx = ADC_TEMP_SENSOR_2_CPU_VR
},
[TEMP_SENSOR_3_WIFI] = {
.name = "WIFI",
.type = TEMP_SENSOR_TYPE_BOARD,
.read = get_temp_3v3_30k9_47k_4050b,
.idx = ADC_TEMP_SENSOR_3_WIFI
},
[TEMP_SENSOR_4_DIMM] = {
.name = "DIMM",
.type = TEMP_SENSOR_TYPE_BOARD,
.read = get_temp_3v3_30k9_47k_4050b,
.idx = ADC_TEMP_SENSOR_4_DIMM
},
};
BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
/*
* TODO(b/180681346): update for Alder Lake/brya
*
* Tiger Lake specifies 100 C as maximum TDP temperature. THRMTRIP# occurs at
* 130 C. However, sensor is located next to DDR, so we need to use the lower
* DDR temperature limit (85 C)
*/
/*
* TODO(b/202062363): Remove when clang is fixed.
*/
#define THERMAL_CPU \
{ \
.temp_host = { \
[EC_TEMP_THRESH_WARN] = 0, \
[EC_TEMP_THRESH_HIGH] = C_TO_K(95), \
[EC_TEMP_THRESH_HALT] = C_TO_K(100), \
}, \
.temp_host_release = { \
[EC_TEMP_THRESH_WARN] = 0, \
[EC_TEMP_THRESH_HIGH] = C_TO_K(90), \
[EC_TEMP_THRESH_HALT] = C_TO_K(90), \
}, \
.temp_fan_off = C_TO_K(35), \
.temp_fan_max = C_TO_K(65), \
}
__maybe_unused static const struct ec_thermal_config thermal_cpu = THERMAL_CPU;
/*
* TODO(b/197478860): add the thermal sensor setting
*/
/* this should really be "const" */
struct ec_thermal_config thermal_params[] = {
[TEMP_SENSOR_1_CPU] = THERMAL_CPU,
[TEMP_SENSOR_2_CPU_VR] = THERMAL_CPU,
[TEMP_SENSOR_3_WIFI] = THERMAL_CPU,
[TEMP_SENSOR_4_DIMM] = THERMAL_CPU,
};
BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
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