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/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Plankton board configuration */
#ifndef __BOARD_H
#define __BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
/* the UART console is on USART2 (PA14/PA15) */
#undef CONFIG_UART_CONSOLE
#define CONFIG_UART_CONSOLE 2
/* Optional features */
#define CONFIG_STM_HWTIMER32
#define CONFIG_USB_POWER_DELIVERY
#define CONFIG_USB_PD_DUAL_ROLE
#define CONFIG_USB_PD_INTERNAL_COMP
#define CONFIG_USB_PD_DYNAMIC_SRC_CAP
#define CONFIG_ADC
#define CONFIG_HW_CRC
#define CONFIG_I2C
#define CONFIG_IO_EXPANDER_PCA9534
#undef CONFIG_WATCHDOG_HELP
#undef CONFIG_LID_SWITCH
#undef CONFIG_TASK_PROFILING
/* I2C ports configuration */
#define I2C_PORT_MASTER 1
/*
* Allow dangerous commands all the time, since we don't have a write protect
* switch.
*/
#define CONFIG_SYSTEM_UNLOCKED
#ifndef __ASSEMBLER__
/* Timer selection */
#define TIM_CLOCK32 2
#define TIM_ADC 3
#include "gpio_signal.h"
/* ADC signal */
enum adc_channel {
ADC_CH_CC1_PD = 0,
ADC_CH_CC2_PD,
/* Number of ADC channels */
ADC_CH_COUNT
};
enum board_src_cap {
SRC_CAP_5V = 0,
SRC_CAP_12V,
SRC_CAP_20V,
};
/* Set USB PD source capability */
void board_set_source_cap(enum board_src_cap cap);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */
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