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/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#ifndef __CROS_EC_REGISTERS_H
#define __CROS_EC_REGISTERS_H
#include "common.h"
#include "gc_regdefs.h"
#include "util.h"
/* Replace masked bits with val << lsb */
#define REG_WRITE_MLV(reg, mask, lsb, val) reg = ((reg & ~mask) | ((val << lsb) & mask))
/* Revision */
#define GC_REVISION_STR "A1 20141117_055451"
#define GR_PINMUX_DIOA0_SEL REG32(GC_PINMUX_BASE_ADDR + GC_PINMUX_DIOA0_SEL_OFFSET)
#define GR_PINMUX_DIOA0_CTL REG32(GC_PINMUX_BASE_ADDR + GC_PINMUX_DIOA0_CTL_OFFSET)
#define GR_PINMUX_DIOA1_SEL REG32(GC_PINMUX_BASE_ADDR + GC_PINMUX_DIOA1_SEL_OFFSET)
#define GR_PINMUX_DIOA1_CTL REG32(GC_PINMUX_BASE_ADDR + GC_PINMUX_DIOA1_CTL_OFFSET)
#define GR_PINMUX_UART0_RX_SEL REG32(GC_PINMUX_BASE_ADDR + GC_PINMUX_UART0_RX_SEL_OFFSET)
#define GR_PINMUX_UART0_TX_SEL REG32(GC_PINMUX_BASE_ADDR + GC_PINMUX_UART0_TX_SEL_OFFSET)
#define GR_PMU_CLRDIS REG32(GC_PMU_BASE_ADDR + GC_PMU_CLRDIS_OFFSET)
#define GR_PMU_OSC_HOLD_SET REG32(GC_PMU_BASE_ADDR + GC_PMU_OSC_HOLD_SET_OFFSET)
#define GR_PMU_OSC_HOLD_CLR REG32(GC_PMU_BASE_ADDR + GC_PMU_OSC_HOLD_CLR_OFFSET)
#define GR_PMU_OSC_SELECT REG32(GC_PMU_BASE_ADDR + GC_PMU_OSC_SELECT_OFFSET)
#define GR_PMU_OSC_SELECT_STAT REG32(GC_PMU_BASE_ADDR + GC_PMU_OSC_SELECT_STAT_OFFSET)
#define GR_PMU_OSC_CTRL REG32(GC_PMU_BASE_ADDR + GC_PMU_OSC_CTRL_OFFSET)
#define GR_PMU_PERICLKSET0 REG32(GC_PMU_BASE_ADDR + GC_PMU_PERICLKSET0_OFFSET)
#define GR_PMU_FUSE_RD_RC_OSC_26MHZ REG32(GC_PMU_BASE_ADDR + GC_PMU_FUSE_RD_RC_OSC_26MHZ_OFFSET)
#define GR_PMU_FUSE_RD_XTL_OSC_26MHZ REG32(GC_PMU_BASE_ADDR + GC_PMU_FUSE_RD_XTL_OSC_26MHZ_OFFSET)
/* More than one UART */
BUILD_ASSERT(GC_UART1_BASE_ADDR - GC_UART0_BASE_ADDR == GC_UART2_BASE_ADDR - GC_UART1_BASE_ADDR);
#define X_UART_BASE_ADDR_SEP (GC_UART1_BASE_ADDR - GC_UART0_BASE_ADDR)
static inline int x_uart_addr(int ch, int offset)
{
return offset + GC_UART0_BASE_ADDR + X_UART_BASE_ADDR_SEP * ch;
}
#define X_UARTREG(ch, offset) REG32(x_uart_addr(ch, offset))
#define GR_UART_RDATA(ch) X_UARTREG(ch, GC_UART_RDATA_OFFSET)
#define GR_UART_WDATA(ch) X_UARTREG(ch, GC_UART_WDATA_OFFSET)
#define GR_UART_NCO(ch) X_UARTREG(ch, GC_UART_NCO_OFFSET)
#define GR_UART_CTRL(ch) X_UARTREG(ch, GC_UART_CTRL_OFFSET)
#define GR_UART_ICTRL(ch) X_UARTREG(ch, GC_UART_ICTRL_OFFSET)
#define GR_UART_STATE(ch) X_UARTREG(ch, GC_UART_STATE_OFFSET)
#define GR_UART_STATECLR(ch) X_UARTREG(ch, GC_UART_STATECLR_OFFSET)
#define GR_UART_ISTATE(ch) X_UARTREG(ch, GC_UART_ISTATE_OFFSET)
#define GR_UART_ISTATECLR(ch) X_UARTREG(ch, GC_UART_ISTATECLR_OFFSET)
#define GR_UART_FIFO(ch) X_UARTREG(ch, GC_UART_FIFO_OFFSET)
#define GR_UART_RFIFO(ch) X_UARTREG(ch, GC_UART_RFIFO_OFFSET)
/*
* High-speed timers. Two modules with two timers each; four timers total.
*/
#define X_TIMEHS_BASE_ADDR_SEP (GC_TIMEHS1_BASE_ADDR - GC_TIMEHS0_BASE_ADDR)
#define X_TIMEHSX_TIMER_OFS_SEP (GC_TIMEHS_TIMER2LOAD_OFFSET - GC_TIMEHS_TIMER1LOAD_OFFSET)
/* NOTE: module is 0-1, timer is 1-2 */
static inline int x_timehs_addr(unsigned int module, unsigned int timer,
int offset)
{
return GC_TIMEHS0_BASE_ADDR + X_TIMEHS_BASE_ADDR_SEP * module
+ GC_TIMEHS_TIMER1LOAD_OFFSET + X_TIMEHSX_TIMER_OFS_SEP * (timer - 1)
+ offset;
}
/* Per-timer registers */
#define X_TIMEHSREG(m, t, ofs) REG32(x_timehs_addr(m, t, ofs))
#define GR_TIMEHS_LOAD(m, t) X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1LOAD_OFFSET)
#define GR_TIMEHS_VALUE(m, t) X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1VALUE_OFFSET)
#define GR_TIMEHS_CONTROL(m, t) X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1CONTROL_OFFSET)
#define GR_TIMEHS_INTCLR(m, t) X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1INTCLR_OFFSET)
#define GR_TIMEHS_RIS(m, t) X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1RIS_OFFSET)
#define GR_TIMEHS_MIS(m, t) X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1MIS_OFFSET)
#define GR_TIMEHS_BGLOAD(m, t) X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1BGLOAD_OFFSET)
/* Watchdog */
#define GR_WDOG_REG(off) REG32(GC_WATCHDOG0_BASE_ADDR + (off))
#define GR_WATCHDOG_LOAD GR_WDOG_REG(GC_WATCHDOG_WDOGLOAD_OFFSET)
#define GR_WATCHDOG_VALUE GR_WDOG_REG(GC_WATCHDOG_WDOGVALUE_OFFSET)
#define GR_WATCHDOG_CTL GR_WDOG_REG(GC_WATCHDOG_WDOGCONTROL_OFFSET)
#define GR_WATCHDOG_ICR GR_WDOG_REG(GC_WATCHDOG_WDOGINTCLR_OFFSET)
#define GR_WATCHDOG_RIS GR_WDOG_REG(GC_WATCHDOG_WDOGRIS_OFFSET)
#define GR_WATCHDOG_LOCK GR_WDOG_REG(GC_WATCHDOG_WDOGLOCK_OFFSET)
#define GR_WATCHDOG_ITCR GR_WDOG_REG(GC_WATCHDOG_WDOGITCR_OFFSET)
#define GR_WATCHDOG_ITOP GR_WDOG_REG(GC_WATCHDOG_WDOGITOP_OFFSET)
/* Oscillator */
#define GR_XO_OSC_CLKOUT REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_CLKOUT_OFFSET)
#define GR_XO_OSC_ADC_CAL_FREQ2X REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_ADC_CAL_FREQ2X_OFFSET)
#define GR_XO_OSC_ADC_CAL_FREQ2X_STAT REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_ADC_CAL_FREQ2X_STAT_OFFSET)
#define GR_XO_OSC_24_48B_SEL REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_24_48B_SEL_OFFSET)
#define GR_XO_OSC_TEST REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_TEST_OFFSET)
#define GR_XO_OSC_RC_CAL_RSTB REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_CAL_RSTB_OFFSET)
#define GR_XO_OSC_RC_CAL_LOAD REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_CAL_LOAD_OFFSET)
#define GR_XO_OSC_RC_CAL_START REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_CAL_START_OFFSET)
#define GR_XO_OSC_RC_CAL_DONE REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_CAL_DONE_OFFSET)
#define GR_XO_OSC_RC_CAL_COUNT REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_CAL_COUNT_OFFSET)
#define GR_XO_OSC_RC REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_OFFSET)
#define GR_XO_OSC_RC_STATUS REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_STATUS_OFFSET)
#define GR_XO_OSC_XTL_TRIMD REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_TRIMD_OFFSET)
#define GR_XO_OSC_XTL_TRIMG REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_TRIMG_OFFSET)
#define GR_XO_OSC_XTL_CTRL REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_CTRL_OFFSET)
#define GR_XO_OSC_XTL_RC_FLTR REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_RC_FLTR_OFFSET)
#define GR_XO_OSC_XTL_OVRD REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_OVRD_OFFSET)
#define GR_XO_OSC_XTL_OVRD_HOLDB REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_OVRD_HOLDB_OFFSET)
#define GR_XO_OSC_XTL_TRIM REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_TRIM_OFFSET)
#define GR_XO_OSC_XTL_TRIM_STAT REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_TRIM_STAT_OFFSET)
#define GR_XO_OSC_XTL_FSM_EN REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_FSM_EN_OFFSET)
#define GR_XO_OSC_XTL_FSM REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_FSM_OFFSET)
#define GR_XO_OSC_XTL_FSM_CFG REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_FSM_CFG_OFFSET)
#define GR_XO_OSC_SETHOLD REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_SETHOLD_OFFSET)
#define GR_XO_OSC_CLRHOLD REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_CLRHOLD_OFFSET)
#endif /* __CROS_EC_REGISTERS_H */
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