blob: f323b4568c0354552a001c6d682c17bc900383b4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
|
/* Copyright 2019 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* MAX32660 Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral */
#ifndef _PWRSEQ_REGS_H_
#define _PWRSEQ_REGS_H_
/* **** Includes **** */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ICCARM__)
#pragma system_include
#endif
#if defined(__CC_ARM)
#pragma anon_unions
#endif
/*
If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I volatile const
#endif
#ifndef __O
#define __O volatile
#endif
#ifndef __R
#define __R volatile const
#endif
/* **** Definitions **** */
/**
* mxc_pwrseq_regs_t
* Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral
* Module.
*/
/**
* pwrseq_registers
* Structure type to access the PWRSEQ Registers.
*/
typedef struct {
__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
__IO uint32_t
lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
__R uint32_t rsv_0xc_0x3f[13];
__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
} mxc_pwrseq_regs_t;
/**
* Register offsets for module PWRSEQ
* PWRSEQ Peripheral Register Offsets from the PWRSEQ Base
*/
#define MXC_R_PWRSEQ_LP_CTRL \
((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
\ \ \ 0x0000</tt> */
#define MXC_R_PWRSEQ_LP_WAKEFL \
((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
\ \ \ 0x0004</tt> */
#define MXC_R_PWRSEQ_LPWK_EN \
((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
\ \ \ 0x0008</tt> */
#define MXC_R_PWRSEQ_LPMEMSD \
((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> \ \
\ \ \ 0x0040</tt> */
/**
* pwrseq_registers
* Low Power Control Register.
*/
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS \
0 /**< LP_CTRL_RAMRET_SEL0 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \ \
LP_CTRL_RAMRET_SEL0 \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \
((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \
(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \
<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS \
\ \ \ \ Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \
((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \
(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \
<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN \
\ \ \ \ Setting */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS \
1 /**< LP_CTRL_RAMRET_SEL1 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \ \
LP_CTRL_RAMRET_SEL1 \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \
((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \
(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \
<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS \
\ \ \ \ Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \
((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \
(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \
<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN \
\ \ \ \ Setting */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS \
2 /**< LP_CTRL_RAMRET_SEL2 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \ \
LP_CTRL_RAMRET_SEL2 \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \
((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \
(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \
<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS \
\ \ \ \ Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \
((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \
(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \
<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN \
\ \ \ \ Setting */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS \
3 /**< LP_CTRL_RAMRET_SEL3 Position */
#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \ \
LP_CTRL_RAMRET_SEL3 \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \
((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \
(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \
<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS \
\ \ \ \ Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \
((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \
(MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \
<< MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN \
\ \ \ \ Setting */
#define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */
#define MXC_F_PWRSEQ_LP_CTRL_OVR \
((uint32_t)(0x3UL \
<< MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */
#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \
((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V \
(MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \
<< MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \
((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V \
(MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \
<< MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */
#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \
((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */
#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V \
(MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \
<< MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS \
6 /**< LP_CTRL_VCORE_DET_BYPASS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< \ \ \ \ \
LP_CTRL_VCORE_DET_BYPASS \
\ \
\ \ \ \ \
Mask */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \
((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \
(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \
<< MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \
LP_CTRL_VCORE_DET_BYPASS_ENABLED \
\ \ \ \ Setting */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \
((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \
(MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \
<< MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \
LP_CTRL_VCORE_DET_BYPASS_DISABLE \
\ \ \ \ Setting */
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS \
8 /**< LP_CTRL_RETREG_EN Position \ \ \ \ \
*/
#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \
((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS \
(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \
<< MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS \ \ \
\ \ Setting */
#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \
((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN \
(MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \
<< MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \ \
\ \ Setting */
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS \
10 /**< LP_CTRL_FAST_WK_EN Position */
#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \ \
LP_CTRL_FAST_WK_EN \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \
((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \
(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \
<< MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS \ \
\ \ \ Setting */
#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \
((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \
(MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \
<< MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \ \
\ \ \ Setting */
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */
#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF \
((uint32_t)( \
0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \
((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */
#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON \
(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \
<< MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */
#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \
((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */
#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF \
(MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \
<< MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting \ \
* \ \
* \ \ \
* \ \ \ \
*/
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS \
12 /**< LP_CTRL_VCORE_POR_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \ \
LP_CTRL_VCORE_POR_DIS \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \
((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \
(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \
<< MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \
LP_CTRL_VCORE_POR_DIS_DIS \
\ \ \ \ Setting */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \
((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \
(MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \
<< MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \
LP_CTRL_VCORE_POR_DIS_EN \
\ \ \ \ Setting */
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS \
((uint32_t)(0x1UL \
<< MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \
((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN \
(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \
<< MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting \
* \ \
* \ \ \
* \ \ \ \
* \ \ \ \ \
*/
#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \
((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS \
(MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \
<< MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting \
* \ \
* \ \ \
* \ \ \ \
* \ \ \ \ \
*/
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS \
20 /**< LP_CTRL_VCORE_SVM_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \ \
LP_CTRL_VCORE_SVM_DIS \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \
((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \
(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \
<< MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \
LP_CTRL_VCORE_SVM_DIS_EN \
\ \ \ \ Setting */
#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \
((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \
(MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \
<< MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \
LP_CTRL_VCORE_SVM_DIS_DIS \
\ \ \ \ Setting */
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS \
25 /**< LP_CTRL_VDDIO_POR_DIS Position */
#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \ \
LP_CTRL_VDDIO_POR_DIS \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \
((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */
#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \
(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \
<< MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \
LP_CTRL_VDDIO_POR_DIS_EN \
\ \ \ \ Setting */
#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \
((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */
#define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \
(MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \
<< MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \
LP_CTRL_VDDIO_POR_DIS_DIS \
\ \ \ \ Setting */
/**
* pwrseq_registers
* Low Power Mode Wakeup Flags for GPIO0
*/
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */
#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST \
((uint32_t)( \
0x3FFFUL \
<< MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST \ \
\ \ \ Mask */
/**
* pwrseq_registers
* Low Power I/O Wakeup Enable Register 0. This register enables low
* power wakeup functionality for GPIO0.
*/
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */
#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN \
((uint32_t)(0x3FFFUL \
<< MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN \ \
\ \ \ Mask */
/**
* pwrseq_registers
* Low Power Memory Shutdown Control.
*/
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS \
0 /**< LPMEMSD_SRAM0_OFF Position \ \ \ \ \
*/
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \
((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \
(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \
<< MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL \
\ \ \ \ Setting */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \
((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \
(MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \
<< MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \ \
LPMEMSD_SRAM0_OFF_SHUTDOWN \
\ \ \ \ Setting */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS \
1 /**< LPMEMSD_SRAM1_OFF Position \ \ \ \ \
*/
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \
((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \
(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \
<< MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL \
\ \ \ \ Setting */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \
((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \
(MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \
<< MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \ \
LPMEMSD_SRAM1_OFF_SHUTDOWN \
\ \ \ \ Setting */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS \
2 /**< LPMEMSD_SRAM2_OFF Position \ \ \ \ \
*/
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \
((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \
(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \
<< MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL \
\ \ \ \ Setting */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \
((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \
(MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \
<< MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \ \
LPMEMSD_SRAM2_OFF_SHUTDOWN \
\ \ \ \ Setting */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS \
3 /**< LPMEMSD_SRAM3_OFF Position \ \ \ \ \
*/
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF \
((uint32_t)( \
0x1UL \
<< MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF \
\ \ \ \ Mask */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \
((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \
(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \
<< MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL \
\ \ \ \ Setting */
#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \
((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */
#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \
(MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \
<< MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \ \
LPMEMSD_SRAM3_OFF_SHUTDOWN \
\ \ \ \ Setting */
#ifdef __cplusplus
}
#endif
#endif /* _PWRSEQ_REGS_H_ */
|
