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/* Copyright 2022 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/dts-v1/;
#include <cros/nuvoton/npcx7.dtsi>
#include <dt-bindings/gpio_defines.h>
#include <dt-bindings/gpio/nuvoton-npcx-gpio.h>
#include <nuvoton/npcx7m7fc.dtsi>
#include <nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi>
#define GPIO_VOLTAGE_1P8 NPCX_GPIO_VOLTAGE_1P8
/ {
model = "NPCX7";
aliases {
i2c-0 = &i2c0_0;
i2c-1 = &i2c1_0;
i2c-2 = &i2c2_0;
i2c-3 = &i2c3_0;
i2c-5 = &i2c5_0;
i2c-7 = &i2c7_0;
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart1;
zephyr,shell-uart = &uart1;
zephyr,flash = &flash0;
zephyr,flash-controller = &int_flash;
cros,rtc = &mtc;
};
named-i2c-ports {
compatible = "named-i2c-ports";
};
named-adc-channels {
compatible = "named-adc-channels";
};
/* Override keyboard scanning */
soc {
/delete-node/ kscan@400a3000;
};
};
&uart1 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart1_2_sin_sout_gp64_65>;
pinctrl-names = "default";
};
&pinctrl {
/*
* TODO(b/232573074): Move pinctrl to set SHI pins to GPIO mode
* upstream.
*/
/omit-if-no-ref/ shi_gpio_gp46_47_53_55: periph-shi-gpio {
pinmux = <&altc_shi_sl>;
pinmux-gpio;
};
};
&cros_kb_raw {
status = "okay";
/* No KSO2 (it's inverted and implemented by GPIO) */
pinctrl-0 = <&ksi0_gp31
&ksi1_gp30
&ksi2_gp27
&ksi3_gp26
&ksi4_gp25
&ksi5_gp24
&ksi6_gp23
&ksi7_gp22
&kso00_gp21
&kso01_gp20
&kso03_gp16
&kso04_gp15
&kso05_gp14
&kso06_gp13
&kso07_gp12
&kso08_gp11
&kso09_gp10
&kso10_gp07
&kso11_gp06
&kso12_gp05
>;
pinctrl-names = "default";
};
/* PSL_OUT is fixed to GPIO85 in npcx7 series. */
&power_ctrl_psl {
enable-gpios = <&gpio8 5 0>;
};
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