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/*
* Copyright (c) 2021 The Chromium OS Authors
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <cros/binman.dtsi>
#include <nuvoton/npcx.dtsi>
/ {
named-bbram-regions {
compatible = "named-bbram-regions";
scratchpad {
offset = <0x00>;
size = <0x04>;
};
saved-reset-flags {
offset = <0x04>;
size = <0x04>;
};
wake {
offset = <0x08>;
size = <0x04>;
};
pd0 {
offset = <0x0c>;
size = <0x01>;
};
pd1 {
offset = <0x0d>;
size = <0x01>;
};
try_slot {
offset = <0x0e>;
size = <0x01>;
};
pd2 {
offset = <0x0f>;
size = <0x01>;
};
ramlog {
offset = <0x20>;
size = <0x01>;
};
panic_flags {
offset = <0x23>;
size = <0x01>;
};
panic_bkup {
offset = <0x24>;
size = <0x1c>;
};
lct_time {
offset = <0x40>;
size = <0x04>;
};
};
soc {
bbram: bb-ram@400af000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "nuvoton,npcx-cros-bbram";
status = "okay";
reg = <0x400af000 0x80
0x400af100 0x1>;
reg-names = "memory", "status";
label = "BBRAM";
};
cros_kb_raw: cros-kb-raw@400a3000 {
compatible = "nuvoton,npcx-cros-kb-raw";
reg = <0x400a3000 0x2000>;
label = "CROS_KB_RAW_0";
interrupts = <49 4>;
clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>;
/*
* No KSO2 (It's inverted and implemented by GPIO for
* CONFIG_KEYBOARD_COL2_INVERTED.)
*/
pinctrl-0 = <&alt7_no_ksi0_sl
&alt7_no_ksi1_sl
&alt7_no_ksi2_sl
&alt7_no_ksi3_sl
&alt7_no_ksi4_sl
&alt7_no_ksi5_sl
&alt7_no_ksi6_sl
&alt7_no_ksi7_sl
&alt8_no_kso00_sl
&alt8_no_kso01_sl
&alt8_no_kso03_sl
&alt8_no_kso04_sl
&alt8_no_kso05_sl
&alt8_no_kso06_sl
&alt8_no_kso07_sl
&alt9_no_kso08_sl
&alt9_no_kso09_sl
&alt9_no_kso10_sl
&alt9_no_kso11_sl
&alt9_no_kso12_sl
&alt9_no_kso13_sl
&alt9_no_kso14_sl
&alt9_no_kso15_sl
&alta_no_kso16_sl
&alta_no_kso17_sl
>;
wui_maps = <&wui_io31 &wui_io30 &wui_io27 &wui_io26
&wui_io25 &wui_io24 &wui_io23 &wui_io22>;
};
mtc: mtc@400b7000 {
compatible = "nuvoton,npcx-cros-mtc";
reg = <0x400b7000 0x2000>;
mtc-alarm = <&wui_mtc>;
label = "MTC";
};
fiu0: cros-flash@40020000 {
compatible = "nuvoton,npcx-cros-flash";
reg = <0x40020000 0x2000>;
clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL1 2>;
size = <0x80000>;
label = "FLASH_INTERFACE_UNIT0";
pinctrl-0 = <>;
};
shi: shi@4000f000 {
compatible = "nuvoton,npcx-cros-shi";
reg = <0x4000f000 0x120>;
interrupts = <18 1>;
clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>;
pinctrl-0 = <&altc_shi_sl>;
shi-cs-wui =<&wui_io53>;
label = "SHI";
};
};
};
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