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/* Copyright 2022 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/ {
chosen {
intel-ap-pwrseq,espi = &espi0;
};
common-pwrseq {
compatible = "intel,ap-pwrseq";
sys-pwrok-delay = <3>;
all-sys-pwrgd-timeout = <20>;
};
pwr-en-pp3300-s5 {
compatible = "intel,ap-pwrseq-gpio";
dbg-label = "PP3300_S5 enable output to LS";
enum-name = "PWR_EN_PP3300_A";
gpios = <&gpioc 4 0>;
output;
};
pwr-pg-ec-rsmrst-od {
compatible = "intel,ap-pwrseq-gpio";
dbg-label = "RSMRST power good from regulator";
enum-name = "PWR_RSMRST";
gpios = <&gpio6 6 0>;
interrupt-flags = <GPIO_INT_EDGE_BOTH>;
};
pwr-ec-pch-rsmrst-odl {
compatible = "intel,ap-pwrseq-gpio";
dbg-label = "RSMRST output to PCH";
enum-name = "PWR_EC_PCH_RSMRST";
gpios = <&gpioa 4 0>;
output;
};
pwr-slp-s0-l {
compatible = "intel,ap-pwrseq-gpio";
dbg-label = "SLP_S0_L input from PCH";
enum-name = "PWR_SLP_S0";
gpios = <&gpioa 1 GPIO_ACTIVE_LOW>;
interrupt-flags = <GPIO_INT_EDGE_BOTH>;
};
pwr-pch-pwrok {
compatible = "intel,ap-pwrseq-gpio";
dbg-label = "PCH_PWROK output to PCH";
enum-name = "PWR_PCH_PWROK";
gpios = <&gpiod 3 GPIO_OPEN_DRAIN>;
output;
};
pwr-ec-pch-sys-pwrok {
compatible = "intel,ap-pwrseq-gpio";
dbg-label = "SYS_PWROK output to PCH";
enum-name = "PWR_EC_PCH_SYS_PWROK";
gpios = <&gpiof 5 GPIO_OPEN_DRAIN>;
output;
};
pwr-sys-rst-l {
compatible = "intel,ap-pwrseq-gpio";
dbg-label = "SYS_RESET# output to PCH";
enum-name = "PWR_SYS_RST";
gpios = <&gpioc 5 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>;
output;
};
pwr-slp-s3 {
compatible = "intel,ap-pwrseq-vw";
dbg-label = "SLP_S3 virtual wire input from PCH";
enum-name = "PWR_SLP_S3";
virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S3";
vw-invert;
};
pwr-slp-s4 {
compatible = "intel,ap-pwrseq-vw";
dbg-label = "SLP_S4 virtual wire input from PCH";
enum-name = "PWR_SLP_S4";
virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4";
vw-invert;
};
pwr-slp-s5 {
compatible = "intel,ap-pwrseq-vw";
dbg-label = "SLP_S5 virtual wire input from PCH";
enum-name = "PWR_SLP_S5";
virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5";
vw-invert;
};
pwr-all-sys-pwrgd {
compatible = "intel,ap-pwrseq-gpio";
dbg-label = "all power good";
enum-name = "PWR_ALL_SYS_PWRGD";
gpios = <&gpio7 0 0>;
interrupt-flags = <GPIO_INT_EDGE_BOTH>;
};
};
/*
* Because the power signals directly reference the GPIOs,
* the correspinding named-gpios need to have no-auto-init set.
*/
&en_pp3300_a {
no-auto-init;
};
&rsmrst_pwrgd {
no-auto-init;
};
&ec_pch_rsmrst_l {
no-auto-init;
};
&pch_slp_s0_n {
no-auto-init;
};
&ec_pch_pwrok_od {
no-auto-init;
};
&sys_pwrok_ec {
no-auto-init;
};
&sys_rst_odl {
no-auto-init;
};
&all_sys_pwrgd {
no-auto-init;
};
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