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/* Copyright 2022 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include <board-overlays/native_posix.dts>
#include <cros/binman.dtsi>
#include <dt-bindings/gpio_defines.h>
#include <freq.h>
/ {
chosen {
cros-ec,espi = &espi0;
intel-ap-pwrseq,espi = &espi0;
};
/*
* Keep these GPIOs in pin order.
* If you need to add one, make sure you increase
* ngpios in the gpio0 node further down.
*/
named-gpios {
compatible = "named-gpios";
gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
/* GPIO_PULL_UP will cause this start asserted,
* i.e. not pressed.
*/
gpios = <&gpio0 1 (GPIO_INPUT | GPIO_PULL_UP)>;
enum-name = "GPIO_POWER_BUTTON_L";
};
gpio_pch_pwrbtn_l: pch_pwrbtn_l {
gpios = <&gpio0 2 GPIO_OUTPUT>;
enum-name = "GPIO_PCH_PWRBTN_L";
};
gpio_ec_pch_wake_odl: ec_pch_wake_odl {
gpios = <&gpio0 3 GPIO_OUTPUT_HIGH>;
};
gpio_lid_open_ec: lid_open_ec {
/* GPIO_PULL_UP will cause this start asserted. */
gpios = <&gpio0 4 (GPIO_INPUT | GPIO_PULL_UP)>;
enum-name = "GPIO_LID_OPEN";
};
};
gpio-interrupts {
compatible = "cros-ec,gpio-interrupts";
int_lid_open_ec: lid_open_ec {
irq-pin = <&gpio_lid_open_ec>;
flags = <GPIO_INT_EDGE_BOTH>;
handler = "lid_interrupt";
};
};
clock: clock {
compatible = "cros,clock-control-emul";
clock-frequency = <DT_FREQ_M(100)>; /* 100 MHz */
};
};
&espi0 {
espi-host@0 {
status = "okay";
compatible = "zephyr,espi-emul-espi-host";
reg = <0x0>;
};
};
&gpio0 {
ngpios = <23>;
};
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