summaryrefslogtreecommitdiff
path: root/zephyr/test/qcom_power/boards/native_posix.overlay
blob: 9af8f4cd13b2a34c1dc05f60d31f9fcf9171e662 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
/* Copyright 2022 The ChromiumOS Authors
 * Use of this source code is governed by a BSD-style license that can be
 * found in the LICENSE file.
 */

#include <board-overlays/native_posix.dts>
#include <dt-bindings/gpio_defines.h>
#include <cros/binman.dtsi>

/ {
	chosen {
		cros-ec,flash-controller = &cros_flash;
	};
	aliases {
		gpio-wp = &gpio_wp_l;
	};
	cros_flash: cros-flash {
		compatible = "cros-ec,flash-emul";
	};

	/*
	 * Keep these GPIOs in pin order.
	 * If you need to add one, make sure you increase
	 * ngpios in the gpio0 node further down.
	 */
	named-gpios {
		compatible = "named-gpios";

		gpio_acok_od: acok_od {
			gpios = <&gpio0 0 GPIO_INPUT>;
			enum-name = "GPIO_AC_PRESENT";
		};
		ec_bl_disable_l {
			gpios = <&gpio0 1 GPIO_INPUT>;
			enum-name = "GPIO_ENABLE_BACKLIGHT";
		};
		gpio_en_pp5000_s5: en_pp5000_s5 {
			gpios = <&gpio0 2 GPIO_OUTPUT_HIGH>;
			enum-name = "GPIO_EN_PP5000";
		};
		gpio_wp_l: wp_l {
			gpios = <&gpio0 3 (GPIO_INPUT | GPIO_ACTIVE_LOW)>;
		};
		gpio_switchcap_pg_int_l: switchcap_pg_int_l {
			gpios = <&gpio0 15 (GPIO_OUTPUT | GPIO_INPUT)>;
		};
		gpio_ap_rst_l: ap_rst_l {
			gpios = <&gpio0 16 GPIO_INPUT>;
			enum-name = "GPIO_AP_RST_L";
		};
		gpio_ps_hold: ps_hold {
			gpios = <&gpio0 17 (GPIO_INPUT | GPIO_PULL_DOWN)>;
			enum-name = "GPIO_PS_HOLD";
		};
		gpio_mb_power_good: mb_power_good {
			gpios = <&gpio0 18 (GPIO_INPUT | GPIO_PULL_DOWN)>;
			enum-name = "GPIO_POWER_GOOD";
		};
		gpio_ap_suspend: ap_suspend {
			gpios = <&gpio0 19 GPIO_INPUT>;
			enum-name = "GPIO_AP_SUSPEND";
		};
		gpio_pmic_kpd_pwr_odl: pmic_kpd_pwr_odl {
			gpios = <&gpio0 20 GPIO_OUTPUT_HIGH>;
			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
		};
		gpio_pmic_resin_l: pmic_resin_l {
			/* Real hardware will allow reading even if GPIO_INPUT
			 * is not set, but the gpio_emul will not.
			 */
			gpios = <&gpio0 21 (GPIO_INPUT | GPIO_OUTPUT_HIGH)>;
			enum-name = "GPIO_PMIC_RESIN_L";
		};
		gpio_warm_reset_l: warm_reset_l {
			gpios = <&gpio0 22 GPIO_INPUT>;
			enum-name = "GPIO_WARM_RESET_L";
		};
		gpio_lid_open_ec: lid_open_ec {
			/* GPIO_PULL_UP will cause this start asserted. */
			gpios = <&gpio0 23 (GPIO_INPUT | GPIO_PULL_UP)>;
			enum-name = "GPIO_LID_OPEN";
		};
		gpio_switchcap_on: switchcap_on {
			gpios = <&gpio0 24 (GPIO_INPUT | GPIO_OUTPUT_LOW)>;
		};
		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
			/* GPIO_PULL_UP will cause this start asserted,
			 * i.e. not pressed.
			 */
			gpios = <&gpio0 25 (GPIO_INPUT | GPIO_PULL_UP)>;
			enum-name = "GPIO_POWER_BUTTON_L";
		};
		gpio_switchcap_pg: src_vph_pwr_pg {
			gpios = <&gpio0 26 GPIO_INPUT_PULL_DOWN>;
			enum-name = "GPIO_SWITCHCAP_PG";
		};
	};

	gpio-interrupts {
		compatible = "cros-ec,gpio-interrupts";

		int_ap_rst: ap_rst {
			irq-pin = <&gpio_ap_rst_l>;
			flags = <GPIO_INT_EDGE_BOTH>;
			handler = "chipset_ap_rst_interrupt";
		};
		int_lid_open_ec: lid_open_ec {
			irq-pin = <&gpio_lid_open_ec>;
			flags = <GPIO_INT_EDGE_BOTH>;
			handler = "lid_interrupt";
		};
		int_mb_power_good: mb_power_good {
			irq-pin = <&gpio_mb_power_good>;
			flags = <GPIO_INT_EDGE_BOTH>;
			handler = "power_signal_interrupt";
		};
		int_ap_suspend: ap_suspend {
			irq-pin = <&gpio_ap_suspend>;
			flags = <GPIO_INT_EDGE_BOTH>;
			handler = "power_signal_interrupt";
		};
		int_power_button: power_button {
			irq-pin = <&gpio_ec_pwr_btn_odl>;
			flags = <GPIO_INT_EDGE_BOTH>;
			handler = "power_button_interrupt";
		};
	};

	gpio1: gpio@101 {
		status = "okay";
		compatible = "zephyr,gpio-emul";
		reg = <0x101 0x4>;
		rising-edge;
		falling-edge;
		high-level;
		low-level;
		gpio-controller;
		#gpio-cells = <2>;
		ngpios = <7>;
	};

	switchcap {
		compatible = "cros-ec,switchcap-gpio";
		enable-pin = <&gpio_switchcap_on>;
		power-good-pin = <&gpio_switchcap_pg>;
		poff-delay-ms = <1>;
	};
};

&gpio0 {
	ngpios = <32>;
};