delta/coreboot/coreboot.git/src/cpu/x86, branch master

cpu/x86/mp_init.c: Set topology on BSP

2023-04-13T11:32:38+00:00

The BSP might have non-zero lapicid so set the topology accordingly,
without assuming it is 0. This fixes a cpu exception on at least Intel
Meteorlake. This was caused by FSP CPU PPI being giving incorrect
information about the BSP topology.

This problem was introduced by 8b8400a "drivers/fsp2_0/mp_service_ppi:
Use struct device to fill in buffer" which sets the PPI struct based on
struct device.

TESTED on google/rex

Change-Id: I3fae5efa86d8efc474c129b48bdfa1d1e2306acf
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74374
Reviewed-by: Subrata Banik 
Reviewed-by: Kapil Porwal 
Reviewed-by: Tarun Tuli 
Tested-by: build bot (Jenkins)

cpu/x86/topology: Add code to fill in topology on struct path

2023-04-06T15:27:23+00:00

This is needed to generate MADT and SRAT where lapicid for threads need
to be added last. When CPUID leaf '0xB' is not present assume some
defaults that would result in identical ACPI code generation.

Change-Id: I2210eb9b663dd90941a64132aa7154440dc7e5a9
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69222
Reviewed-by: Maximilian Brune 
Reviewed-by: Patrick Rudolph 
Tested-by: build bot (Jenkins)

cpu/mp_init.c: Only enable CPUs once they execute code

2023-04-06T15:27:02+00:00

On some systems the BSP cannot know how many CPUs are present in the
system. A typical use case is a multi socket system. Setting the enable
flag only on CPUs that actually exist makes it more flexible.

Change-Id: I6c8042b4d6127239175924f996f735bf9c83c6e8
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68892
Reviewed-by: Angel Pons 
Reviewed-by: Patrick Rudolph 
Tested-by: build bot (Jenkins)

cpu/smm_module_loader.c: Fix up CPU index locally

2023-04-06T15:21:20+00:00

Don't pass the stub params to the mp_init code.

Change-Id: I070bc00ae5e5bceb6c5b90ea833cc057dd41f6cc
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64802
Reviewed-by: Patrick Rudolph 
Tested-by: build bot (Jenkins)

cpu/x86/mp_init.c: Generate a C header to get start32 offset

2023-04-06T15:19:00+00:00

In the current design the relocatable parameters are used to know the
offset of the 32bit startpoint. This requires back and forward
interaction between the stub, the loader and the mp init code. This
makes the code hard to read.

This is static information known at buildtime, so a better way to deal
with this is to generate a header that contains this offset.

Change-Id: Ic01badd2af11a6e1dbc27c8e928916fedf104b5b
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64625
Reviewed-by: Patrick Rudolph 
Reviewed-by: Maximilian Brune 
Tested-by: build bot (Jenkins)

cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_path

2023-04-06T15:13:28+00:00

It's quite confusing to keep track of lapic ID inside the device
struct and initial lapic ID inside an array.

Change-Id: I4d9f8d23c0b0e5c142f6907593428d8509e4e7bb
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64342
Reviewed-by: Maximilian Brune 
Reviewed-by: Patrick Rudolph 
Tested-by: build bot (Jenkins)

cpu/x86/64bit/Makefile: use all_x86 make target

2023-04-04T19:22:33+00:00

Use the newly introduced 'all_x86' make target to add the mode_switch.S
compilation unit to all stages that run on the x86 cores, but not to
verstage on PSP.

Signed-off-by: Felix Held 
Change-Id: I8950375d31557d9a38169869c1d250417261c31c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74197
Tested-by: build bot (Jenkins) 
Reviewed-by: Matt DeVillier

cpu/x86/64bit/Makefile: use verstage_x86 make target

2023-04-04T19:22:08+00:00

Use the 'verstage_x86' make target for the mode_switch.S compilation
unit instead of making adding it to the 'verstage' target depending on
VBOOT_STARTS_BEFORE_BOOTBLOCK not being selected. The only case where
VBOOT_STARTS_BEFORE_BOOTBLOCK is selected is the verstage on PSP case,
so I find using the 'verstage_x86' target here a bit easier to
understand.

Signed-off-by: Felix Held 
Change-Id: Iab618d4b9e325b07a648b91fcdce99c63644fbfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74196
Reviewed-by: Matt DeVillier 
Tested-by: build bot (Jenkins)

cpu/x86/lapic,pae,tsc/Makefile: use all_x86 target

2023-04-04T19:19:58+00:00

Use the newly introduced 'all_x86' make target to add the compilation
unit to all stages that run on the x86 cores, but not to verstage on
PSP.

TEST=Timeless build for Mandolin results in identical image.

Signed-off-by: Felix Held 
Change-Id: I181c3207bb1ebe9c5080ef3a3cdda8146ed05822
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74152
Reviewed-by: Matt DeVillier 
Reviewed-by: Fred Reitberger 
Tested-by: build bot (Jenkins)

cpu/x86/cache: CLFLUSH programs to memory before running

2023-03-13T13:42:32+00:00

When cbmem is initialized in romstage and postcar placed in the stage
cache + cbmem where it is run, the assumption is made that these are
all in UC memory such that calling INVD in postcar is OK.

For performance reasons (e.g. postcar decompression) it is desirable
to cache cbmem and the stage cache during romstage.

Another reason is that AGESA sets up MTRR during romstage to cache all
dram, which is currently worked around by using additional MTRR's to
make that UC.

TESTED on asus/p5ql-em, up/squared on both regular and S3 resume
       bootpath. Sometimes there are minimal performance improvements
       when cbmem is cached (few ms).

Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37196
Reviewed-by: Lean Sheng Tan 
Reviewed-by: Kapil Porwal 
Tested-by: build bot (Jenkins)