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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-11-24 04:06:10 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-26 01:08:25 +0100 |
| commit | 259549678b010c519eac44d459f65ff81d412a34 (patch) | |
| tree | 43fe50811191ad162a1831e1bdfc17dbd04c4de0 | |
| parent | eda407f4ebbc694ac372fa1cc12d6b00f0135b69 (diff) | |
| download | coreboot-259549678b010c519eac44d459f65ff81d412a34.tar.gz | |
mainboard/asus/kgpe-d16: Add missing IOMMU setup
Change-Id: I9a00bdbcd47804b6d83c0231cd515773d02ff951
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12527
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/mainboard/asus/kgpe-d16/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/asus/kgpe-d16/romstage.c | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index ef7277d1d7..014a35f2f4 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -15,6 +15,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex chip southbridge/amd/sr5650 # Primary southbridge device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 on end # CLKCONFIG + device pci 0.2 on end # IOMMU device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) # Slot # PCI E 1 / PCI E 2 end diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 6503b90343..ccb85f4044 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -458,6 +458,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) die("After soft_reset_x - shouldn't see this message!!!\n"); } + sr5650_htinit_dect_and_enable_isochronous_link(); + /* Set default DDR memory voltage * This will be overridden later during RAM initialization */ |