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authorFelix Held <felix-coreboot@felixheld.de>2022-02-11 18:25:04 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-02-25 00:44:45 +0000
commit26f031031719aa9cc7fb4cc7bdfc53af36589341 (patch)
treebb6bb2b20f4d0c6956802e81549d0317fa1fa9f9
parent9ec4bf2fcb694f5dc453b5ad19a94878290fc5eb (diff)
downloadcoreboot-26f031031719aa9cc7fb4cc7bdfc53af36589341.tar.gz
mb/amd/chausie/devicetree: add i2c_scl_reset
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23ec6bcb6a2b3627866165972fd6ba1c75367533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62188 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/amd/chausie/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb
index 53dea43339..1d4d9dae1e 100644
--- a/src/mainboard/amd/chausie/devicetree.cb
+++ b/src/mainboard/amd/chausie/devicetree.cb
@@ -13,6 +13,9 @@ chip soc/amd/sabrina
.flash_ch_en = 0,
}"
+ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
+ GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+
# I2C Pad Control RX Select Configuration
register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"