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authorJohn Su <john_su@compal.corp-partner.google.com>2023-01-06 18:07:57 +0800
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2023-01-12 05:02:33 +0000
commit8afb45e0a67581b5f8cd6a828bbd1daf54825a36 (patch)
tree24a63ea4048d2347eb9e967dd5fd5dc57c596414
parent2626b3eab47becb8002cc393b02bd9b4ee1ae33b (diff)
downloadcoreboot-8afb45e0a67581b5f8cd6a828bbd1daf54825a36.tar.gz
mb/google/skyrim/var/markarth: Update devicetree setting
Update devicetree based on the schematic_20230105. BUG=b:263534907, b:263216451 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I437425ac4a7cdb883dc213f5f6bb5f8a33a5577b Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71714 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
-rw-r--r--src/mainboard/google/skyrim/variants/markarth/overridetree.cb116
1 files changed, 115 insertions, 1 deletions
diff --git a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb
index 7a56f93759..f8e5268aea 100644
--- a/src/mainboard/google/skyrim/variants/markarth/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/markarth/overridetree.cb
@@ -1,5 +1,119 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip soc/amd/mendocino
- device domain 0 on end
+
+ device domain 0 on
+ device ref gpp_bridge_1 on
+ # Required so the NVMe gets placed into D3 when entering S0i3.
+ chip drivers/pcie/rtd3/device
+ register "name" = ""NVME""
+ device pci 00.0 on end
+ end
+ end # NVME
+ device ref gpp_bridge_2 on
+ # Required so the NVMe gets placed into D3 when entering S0i3.
+ chip drivers/pcie/rtd3/device
+ register "name" = ""NVME""
+ device pci 00.0 on end
+ end
+ end # NVME
+
+ device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
+ device ref xhci_1 on # XHCI1 controller
+ chip drivers/usb/acpi
+ device ref xhci_1_root_hub on # XHCI1 root hub
+ chip drivers/usb/acpi
+ device ref usb3_port3 on # USB 3.1 port3
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A0 (MLB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(2, 2))"
+ device usb 3.1 on end
+ end
+ end # USB 3.1 port3
+ end
+ chip drivers/usb/acpi
+ device ref usb2_port3 on # USB 2 port3
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A0 (MLB)""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(2, 2))"
+ device usb 2.1 on end
+ end
+ end # USB 2 port3
+ end
+ end # XHCI1 root hub
+ end
+ end # XHCI1 controller
+ end # Internal GPP Bridge 0 to Bus A
+ end # domain
+
+ device ref i2c_0 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
+ register "wake" = "GEVENT_20"
+ register "detect" = "1"
+ device i2c 15 on end
+ end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""SYNA0000""
+ register "generic.cid" = ""ACPI0C50""
+ register "generic.desc" = ""Synaptics Touchpad""
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_40)"
+ register "generic.wake" = "GEVENT_20"
+ register "generic.detect" = "1"
+ register "hid_desc_reg_offset" = "0x20"
+ device i2c 2c on end
+ end
+ end # I2C0
+ device ref i2c_1 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""ELAN9004""
+ register "generic.desc" = ""ELAN Touchscreen""
+ register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)"
+ register "generic.detect" = "1"
+ register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)"
+ register "generic.enable_delay_ms" = "10"
+ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)"
+ register "generic.reset_off_delay_ms" = "1"
+ register "generic.reset_delay_ms" = "10"
+ register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)"
+ register "generic.stop_delay_ms" = "180"
+ register "generic.stop_off_delay_ms" = "1"
+ register "generic.has_power_resource" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 10 on end
+ end
+ end # I2C1
+ device ref i2c_2 on
+ chip drivers/i2c/generic
+ register "hid" = ""RTL5682""
+ register "name" = ""RT58""
+ register "desc" = ""Realtek RT5682""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)"
+ register "property_count" = "1"
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""10EC1019""
+ register "desc" = ""Realtek SPK AMP R""
+ register "uid" = "1"
+ device i2c 29 on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""10EC1019""
+ register "desc" = ""Realtek SPK AMP L""
+ register "uid" = "2"
+ register "probed" = "1"
+ device i2c 2a on end
+ end
+ end # I2C2
+
end # chip soc/amd/mendocino