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| author | Shobhit Srivastava <shobhit.srivastava@intel.com> | 2015-10-09 17:05:16 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-28 20:40:48 +0100 |
| commit | c4153c1b15fa88796ce3bcccb49e3537c9e65ff3 (patch) | |
| tree | f181ce7d13ea188751a7d39b64c3637b561d4223 | |
| parent | 731e463495b0ebcf16515172b0bded02e318ce9d (diff) | |
| download | coreboot-c4153c1b15fa88796ce3bcccb49e3537c9e65ff3.tar.gz | |
Strago: Enable CA Mirror
Configuring UPD PcdCaMirrorEn. This is a board specific parameter.
CA mirror is the Command Address mirroring option that is enabled
on this board
CQ-DEPEND=CL:13038
Original-Reviewed-on: https://chromium-review.googlesource.com/309190
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I05174e18d650332d838e5036c713e91c4840ee75
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12749
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
| -rwxr-xr-x | src/mainboard/intel/strago/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/soc/intel/braswell/chip.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/braswell/romstage/romstage.c | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index ba8968c14c..91337878c2 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -13,6 +13,7 @@ chip soc/intel/braswell register "PcdApertureSize" = "2" register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" ############################################################ # Set the parameters for SiliconInit diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 7b01f0bf11..e302d6cdf5 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -75,6 +75,7 @@ struct soc_intel_braswell_config { UINT8 PcdGttSize; UINT8 PcdLegacySegDecode; UINT8 PcdDvfsEnable; + UINT8 PcdCaMirrorEn; /* Command Address Mirroring Enabled */ /* * The following fields come from fsp_vpd.h .aka. VpdHeader.h. diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 2581583065..028469a2ca 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -212,6 +212,7 @@ void soc_memory_init_params(struct romstage_params *params, upd->PcdGttSize = config->PcdGttSize; upd->PcdLegacySegDecode = config->PcdLegacySegDecode; upd->PcdDvfsEnable = config->PcdDvfsEnable; + upd->PcdCaMirrorEn = config->PcdCaMirrorEn; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, |