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| author | Damien Zammit <damien@zamaudio.com> | 2016-01-26 17:17:27 +1100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-29 00:28:34 +0100 |
| commit | c70966cd267783e2819418e5d881a2098c476d80 (patch) | |
| tree | e12a226539df1231ecffb16aa845e1b819d8b962 | |
| parent | c4d317f10799fadcd6cf66558f363041106699ae (diff) | |
| download | coreboot-c70966cd267783e2819418e5d881a2098c476d80.tar.gz | |
mb/gigabyte/ga-g41m-es2l: Remove copy-pasted cstates
Change-Id: I5b6edbd97d4e6ed8b03f2f319a338022647e26ea
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13465
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 13 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 3 |
2 files changed, 1 insertions, 15 deletions
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c index dbac2ed020..4d9f4ab456 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c @@ -17,18 +17,7 @@ #include <device/device.h> #include <southbridge/intel/i82801gx/i82801gx.h> -static acpi_cstate_t cst_entries[] = { - { - /* acpi C1 / cpu C1 */ - 1, 0x01, 1000, - { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 } - }, - { - /* acpi C2 / cpu C2 */ - 2, 0x01, 500, - { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } - }, -}; +static acpi_cstate_t cst_entries[] = {}; int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index e6b691c42f..39655387f3 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -21,9 +21,6 @@ chip northbridge/intel/x4x # Northbridge end chip cpu/intel/model_1067x # CPU device lapic 0xACAC off end - register "slfm" = "1" - register "c5" = "1" - register "c6" = "1" end end device domain 0 on # PCI domain |