diff options
| -rw-r--r-- | src/soc/intel/apollolake/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/elog.c | 19 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/xhci.c | 38 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/elog.c | 14 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/xhci.c | 33 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/xhci.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/elog.c | 16 | ||||
| -rw-r--r-- | src/soc/intel/skylake/xhci.c | 33 |
10 files changed, 124 insertions, 45 deletions
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4fc16d5891..6fd0822109 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -44,6 +44,7 @@ smm-y += smihandler.c smm-y += spi.c smm-y += uart.c smm-y += elog.c +smm-y += xhci.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c @@ -67,6 +68,7 @@ ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += xdci.c ramstage-y += sd.c +ramstage-y += xhci.c postcar-y += memmap.c postcar-y += mmap_boot.c diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index c138b346e1..02afb6c5cc 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -25,23 +25,6 @@ #include <soc/smbus.h> #include <stdint.h> -#define XHCI_USB2_PORT_STATUS_REG 0x480 -#if CONFIG(SOC_INTEL_GLK) -#define XHCI_USB3_PORT_STATUS_REG 0x510 -#define XHCI_USB2_PORT_NUM 9 -#else -#define XHCI_USB3_PORT_STATUS_REG 0x500 -#define XHCI_USB2_PORT_NUM 8 -#endif -#define XHCI_USB3_PORT_NUM 7 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -74,7 +57,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) /* XHCI */ if (ps->gpe0_sts[GPE0_A] & XHCI_PME_STS) - pch_xhci_update_wake_event(&usb_info); + pch_xhci_update_wake_event(soc_get_xhci_usb_info()); /* SMBUS Wake */ if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS) diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c new file mode 100644 index 0000000000..131610756f --- /dev/null +++ b/src/soc/intel/apollolake/xhci.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/xhci.h> + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#if CONFIG(SOC_INTEL_GLK) +#define XHCI_USB3_PORT_STATUS_REG 0x510 +#define XHCI_USB2_PORT_NUM 9 +#else +#define XHCI_USB3_PORT_STATUS_REG 0x500 +#define XHCI_USB2_PORT_NUM 8 +#endif +#define XHCI_USB3_PORT_NUM 7 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8a4a8b71f2..7ff86031cb 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -56,12 +56,14 @@ ramstage-y += systemagent.c ramstage-y += uart.c ramstage-y += vr_config.c ramstage-y += sd.c +ramstage-y += xhci.c smm-y += elog.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += xhci.c postcar-y += memmap.c postcar-y += pmutil.c diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 141aa45b02..0bccdb7880 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -24,18 +24,6 @@ #include <soc/pci_devs.h> #include <soc/pm.h> -#define XHCI_USB2_PORT_STATUS_REG 0x480 -#define XHCI_USB3_PORT_STATUS_REG 0x580 -#define XHCI_USB2_PORT_NUM 14 -#define XHCI_USB3_PORT_NUM 10 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -68,7 +56,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) /* XHCI - "Power Management Event Bus 0" events include XHCI */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - pch_xhci_update_wake_event(&usb_info); + pch_xhci_update_wake_event(soc_get_xhci_usb_info()); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) diff --git a/src/soc/intel/cannonlake/xhci.c b/src/soc/intel/cannonlake/xhci.c new file mode 100644 index 0000000000..2741883d88 --- /dev/null +++ b/src/soc/intel/cannonlake/xhci.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/xhci.h> + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x580 +#define XHCI_USB2_PORT_NUM 14 +#define XHCI_USB3_PORT_NUM 10 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index 86b598fda1..492c32a002 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -46,4 +46,14 @@ bool pch_xhci_update_wake_event(const struct xhci_usb_info *info); void soc_xhci_init(struct device *dev); +/** + * soc_get_xhci_usb_info() - Get the information about USB2 & USB3 ports. + * + * This function is used to get USB ports and status register offset information + * within a XHCI controller. + * + * Return: USB ports and status register offset info for the SoC. + */ +const struct xhci_usb_info *soc_get_xhci_usb_info(void); + #endif /* SOC_INTEL_COMMON_BLOCK_XHCI_H */ diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 20fba29116..913a9d9b5d 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -67,6 +67,7 @@ ramstage-y += systemagent.c ramstage-y += thermal.c ramstage-y += uart.c ramstage-y += vr_config.c +ramstage-y += xhci.c smm-y += elog.c smm-y += gpio.c @@ -74,6 +75,7 @@ smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += xhci.c postcar-y += memmap.c postcar-y += gspi.c diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 359f3e612a..47d6137ec7 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -39,18 +39,6 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } -#define XHCI_USB2_PORT_STATUS_REG 0x480 -#define XHCI_USB3_PORT_STATUS_REG 0x540 -#define XHCI_USB2_PORT_NUM 10 -#define XHCI_USB3_PORT_NUM 6 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - struct pme_status_info { #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev; @@ -76,7 +64,7 @@ static void pch_log_add_elog_event(const struct pme_status_info *info, * USB2/3 ports. */ if ((info->dev == PCH_DEV_XHCI) && - pch_xhci_update_wake_event(&usb_info)) + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) return; elog_add_event_wake(info->elog_event, 0); @@ -124,7 +112,7 @@ static void pch_log_pme_internal_wake_source(void) * PME_STS_BIT in controller register. */ if (!dev_found) - dev_found = pch_xhci_update_wake_event(&usb_info); + dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); if (!dev_found) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c new file mode 100644 index 0000000000..bca3b861ea --- /dev/null +++ b/src/soc/intel/skylake/xhci.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/xhci.h> + +#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x540 +#define XHCI_USB2_PORT_NUM 10 +#define XHCI_USB3_PORT_NUM 6 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + +const struct xhci_usb_info *soc_get_xhci_usb_info(void) +{ + return &usb_info; +} |