diff options
56 files changed, 44 insertions, 547 deletions
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index d9098373cd..8c65dae237 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -18,6 +18,7 @@ #include <cbfs.h> #include <console/console.h> #include <arch/cpu.h> +#include <cf9_reset.h> #include <cpu/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> @@ -32,7 +33,6 @@ #include <cbmem.h> #include <program_loading.h> #include <romstage_handoff.h> -#include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> @@ -44,12 +44,6 @@ #include <cpu/intel/romstage.h> #include "haswell.h" -static inline void reset_system(void) -{ - hard_reset(); - halt(); -} - #define ROMSTAGE_RAM_STACK_SIZE 0x5000 /* platform_enter_postcar() determines the stack to use after @@ -147,7 +141,7 @@ void romstage_common(const struct romstage_params *params) } else if (cbmem_initialize()) { #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) /* Failed S3 resume, reset to come up cleanly */ - reset_system(); + system_reset(); #endif } diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 9d3b478f2f..38af2b881b 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -21,6 +21,7 @@ #include <lib.h> #include <timestamp.h> #include <arch/io.h> +#include <cf9_reset.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <cpu/x86/lapic.h> @@ -28,7 +29,6 @@ #include <console/console.h> #include <halt.h> #include <program_loading.h> -#include <reset.h> #include <superio/smsc/sio1007/chip.h> #include <fsp_util.h> #include <northbridge/intel/fsp_sandybridge/northbridge.h> @@ -41,12 +41,6 @@ #define SIO_PORT 0x164e -static inline void reset_system(void) -{ - hard_reset(); - halt(); -} - static void pch_enable_lpc(void) { pci_devfn_t dev = PCH_LPC_DEV; @@ -292,7 +286,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { cbmem_was_initted = !cbmem_recovery(0); if(cbmem_was_initted) { - reset_system(); + system_reset(); } /* Save the HOB pointer in CBMEM to be used in ramstage. */ diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 999d5a812e..fcba7c1457 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -19,12 +19,12 @@ #include <console/console.h> #include <bootstate.h> #include <cbmem.h> +#include <cf9_reset.h> #include <device/device.h> #include <southbridge/intel/fsp_rangeley/pci_devs.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <fspvpd.h> #include <fspbootmode.h> -#include <reset.h> #include "../chip.h" #ifdef __PRE_RAM__ @@ -173,7 +173,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status, *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; if (Status == 0xFFFFFFFF) { - soft_reset(); + system_reset(); } romstage_main_continue(Status, HobListPtr); } diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index eb316555fb..24fdc7497b 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -18,11 +18,11 @@ #include <console/console.h> #include <bootstate.h> #include <cbmem.h> +#include <cf9_reset.h> #include <device/device.h> #include <southbridge_pci_devs.h> #include <fsp_util.h> #include "../chip.h" -#include <reset.h> #ifdef __PRE_RAM__ @@ -97,7 +97,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status, { *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; if (Status == 0xFFFFFFFF) { - hard_reset(); + system_reset(); } romstage_main_continue(Status, HobListPtr); } diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 7b877668cc..66fcded42d 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -17,7 +17,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER - select HAVE_HARD_RESET + select SOUTHBRIDGE_INTEL_COMMON_RESET select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PCIEXP_ASPM diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index ba9517d5dc..324dcdd715 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -23,8 +23,6 @@ smm-y += iosf.c ramstage-y += northcluster.c ramstage-y += ramstage.c ramstage-y += gpio.c -romstage-y += reset.c -ramstage-y += reset.c ramstage-y += cpu.c romstage-y += pmutil.c ramstage-y += pmutil.c diff --git a/src/soc/intel/baytrail/include/soc/reset.h b/src/soc/intel/baytrail/include/soc/reset.h deleted file mode 100644 index 4a36207623..0000000000 --- a/src/soc/intel/baytrail/include/soc/reset.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_RESET_H_ -#define _BAYTRAIL_RESET_H_ -#include <reset.h> - -/* Bay Trail has the following types of resets: - * - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 - * - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 - * - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 - * - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 - * - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but - * with ETR[20] set. - */ - -void cold_reset(void); -void warm_reset(void); - -#endif /* _BAYTRAIL_RESET_H_ */ diff --git a/src/soc/intel/baytrail/reset.c b/src/soc/intel/baytrail/reset.c deleted file mode 100644 index e38a2e6ec8..0000000000 --- a/src/soc/intel/baytrail/reset.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <soc/pmc.h> -#include <soc/reset.h> - -void cold_reset(void) -{ - /* S0->S5->S0 trip. */ - outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); -} - -void warm_reset(void) -{ - /* PMC_PLTRST# asserted. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_soft_reset(void) -{ - /* Sends INIT# to CPU */ - outb(RST_CPU, RST_CNT); -} - -void do_hard_reset(void) -{ - /* Don't power cycle on hard_reset(). It's not really clear what the - * semantics should be for the meaning of hard_reset(). */ - warm_reset(); -} diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 45bc75b9b3..cc055c0dbe 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -18,6 +18,7 @@ #include <assert.h> #include <cbfs.h> #include <cbmem.h> +#include <cf9_reset.h> #include <console/console.h> #include <device/pci_def.h> #include <halt.h> @@ -26,18 +27,11 @@ #include <soc/iomap.h> #include <soc/iosf.h> #include <soc/pci_devs.h> -#include <soc/reset.h> #include <soc/romstage.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <security/vboot/vboot_common.h> -static void reset_system(void) -{ - warm_reset(); - halt(); -} - static void enable_smbus(void) { uint32_t reg; @@ -134,7 +128,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) /* If waking from S3 and no cache then. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); post_code(POST_RESUME_FAILURE); - reset_system(); + system_reset(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); } @@ -165,7 +159,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ - reset_system(); + system_reset(); #endif } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 07b801093f..af67434a92 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -36,7 +36,6 @@ #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pmc.h> -#include <soc/reset.h> #include <soc/romstage.h> #include <soc/smm.h> #include <soc/spi.h> diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index ffd7c7311f..066f1bed48 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -20,7 +20,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER - select HAVE_HARD_RESET + select SOUTHBRIDGE_INTEL_COMMON_RESET select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index c4f45388f8..4e4d3ebe55 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -43,8 +43,6 @@ romstage-y += pmutil.c smm-y += pmutil.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c -ramstage-y += reset.c -romstage-y += reset.c ramstage-y += sata.c ramstage-y += serialio.c ramstage-y += smbus.c diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c deleted file mode 100644 index ad90dcd880..0000000000 --- a/src/soc/intel/broadwell/reset.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <halt.h> -#include <reset.h> -#include <soc/reset.h> - -/* - * Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 - * Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 - * Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 - * Warm reset (PLTRST# assertion) - write 0x6 to I/O 0xcf9 - * Global reset (S0->S5->S0 with ME reset) - write 0x6 or 0xe to 0xcf9 but - * with ETR[20] set. - */ - -void do_soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void do_hard_reset(void) -{ - outb(0x06, 0xcf9); -} - -void reset_system(void) -{ - hard_reset(); - halt(); -} diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 54db3d1564..c4a3b2c9d9 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -18,6 +18,7 @@ #include <assert.h> #include <cbfs.h> #include <cbmem.h> +#include <cf9_reset.h> #include <console/console.h> #include <device/pci_def.h> #include <lib.h> @@ -33,7 +34,6 @@ #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/pm.h> -#include <soc/reset.h> #include <soc/romstage.h> #include <soc/smm.h> #include <soc/systemagent.h> @@ -63,7 +63,7 @@ void raminit(struct pei_data *pei_data) /* Waking from S3 and no cache. */ printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); post_code(POST_RESUME_FAILURE); - reset_system(); + system_reset(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); } @@ -108,7 +108,7 @@ void raminit(struct pei_data *pei_data) #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); /* Failed S3 resume, reset to come up cleanly */ - reset_system(); + system_reset(); #endif } diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index a6691ab9f9..3abc853975 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -32,7 +32,6 @@ #include <soc/me.h> #include <soc/pei_data.h> #include <soc/pm.h> -#include <soc/reset.h> #include <soc/romstage.h> #include <soc/spi.h> diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 2019b6d9a1..7d82f3f49d 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -29,7 +29,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select HAVE_SMI_HANDLER - select HAVE_HARD_RESET + select SOUTHBRIDGE_INTEL_COMMON_RESET select NO_RELOCATABLE_RAMSTAGE select PARALLEL_MP select REG_SCRIPT diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 0cf99dea4c..d8c4f71c32 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -45,8 +45,6 @@ romstage-y += gpio.c romstage-y += pmutil.c ramstage-y += pmutil.c ramstage-y += southcluster.c -romstage-y += reset.c -ramstage-y += reset.c ramstage-y += cpu.c ramstage-y += acpi.c ramstage-y += lpe.c diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index a7268aa20b..c5863f459f 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -19,13 +19,13 @@ #include <console/console.h> #include <bootstate.h> #include <cbmem.h> +#include <cf9_reset.h> #include <device/device.h> #include <device/pci_def.h> #include <soc/pci_devs.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include "../chip.h" #include <arch/io.h> -#include <soc/reset.h> #include <soc/pmc.h> #include <soc/acpi.h> #include <soc/iomap.h> @@ -323,7 +323,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); /* Reboot */ printk(BIOS_WARNING,"Rebooting..\n" ); - warm_reset(); + system_reset(); /* Should not reach here.. */ die("Reboot System\n"); } @@ -343,7 +343,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status, *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; if (Status == 0xFFFFFFFF) { - warm_reset(); + system_reset(); } romstage_main_continue(Status, HobListPtr); } diff --git a/src/soc/intel/fsp_baytrail/include/soc/reset.h b/src/soc/intel/fsp_baytrail/include/soc/reset.h deleted file mode 100644 index 4a36207623..0000000000 --- a/src/soc/intel/fsp_baytrail/include/soc/reset.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _BAYTRAIL_RESET_H_ -#define _BAYTRAIL_RESET_H_ -#include <reset.h> - -/* Bay Trail has the following types of resets: - * - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 - * - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 - * - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 - * - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 - * - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but - * with ETR[20] set. - */ - -void cold_reset(void); -void warm_reset(void); - -#endif /* _BAYTRAIL_RESET_H_ */ diff --git a/src/soc/intel/fsp_baytrail/reset.c b/src/soc/intel/fsp_baytrail/reset.c deleted file mode 100644 index e38a2e6ec8..0000000000 --- a/src/soc/intel/fsp_baytrail/reset.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <soc/pmc.h> -#include <soc/reset.h> - -void cold_reset(void) -{ - /* S0->S5->S0 trip. */ - outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); -} - -void warm_reset(void) -{ - /* PMC_PLTRST# asserted. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_soft_reset(void) -{ - /* Sends INIT# to CPU */ - outb(RST_CPU, RST_CNT); -} - -void do_hard_reset(void) -{ - /* Don't power cycle on hard_reset(). It's not really clear what the - * semantics should be for the meaning of hard_reset(). */ - warm_reset(); -} diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 26c40947a7..ec010b3882 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select HAVE_HARD_RESET + select SOUTHBRIDGE_INTEL_COMMON_RESET select NO_RELOCATABLE_RAMSTAGE select PARALLEL_MP select SMP diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index 931266314c..544819088d 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -23,8 +23,6 @@ ramstage-y += tsc_freq.c romstage-y += memmap.c ramstage-y += memmap.c ramstage-y += southcluster.c -romstage-y += reset.c -ramstage-y += reset.c ramstage-y += acpi.c ramstage-y += smbus_common.c ramstage-y += smbus.c diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index 148ffdc367..800f68653b 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -20,11 +20,11 @@ #include <bootstate.h> #include <cbfs.h> #include <cbmem.h> +#include <cf9_reset.h> #include <device/device.h> #include <device/pci_def.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <soc/pci_devs.h> -#include <soc/reset.h> #include <soc/romstage.h> #include <chip.h> #include <fsp.h> @@ -142,7 +142,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; if (Status == 0xFFFFFFFF) { - warm_reset(); + system_reset(); } romstage_main_continue(Status, HobListPtr); diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/reset.h b/src/soc/intel/fsp_broadwell_de/include/soc/reset.h deleted file mode 100644 index fa0ceac091..0000000000 --- a/src/soc/intel/fsp_broadwell_de/include/soc/reset.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_RESET_H_ -#define _SOC_RESET_H_ - -#include <reset.h> - -void warm_reset(void); - -#endif /* _SOC_RESET_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/reset.c b/src/soc/intel/fsp_broadwell_de/reset.c deleted file mode 100644 index 78d74939e3..0000000000 --- a/src/soc/intel/fsp_broadwell_de/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <soc/reset.h> - -void warm_reset(void) -{ - outb(0x00, 0xcf9); - outb(0x06, 0xcf9); -} - -void do_hard_reset(void) -{ - warm_reset(); -} diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 16602cf883..20cdeb84e3 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -29,7 +29,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select IOAPIC - select HAVE_HARD_RESET select HAVE_USBDEBUG_OPTIONS select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index ea8e96c338..d8730dfdd3 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c ramstage-y += me_status.c -ramstage-y += reset.c ramstage-y += watchdog.c ramstage-$(CONFIG_ELOG) += elog.c @@ -39,7 +38,6 @@ ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c romstage-y += early_smbus.c me_status.c -romstage-y += reset.c romstage-y += early_spi.c early_pch_common.c romstage-y += early_rcba.c diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c deleted file mode 100644 index 7faadb62df..0000000000 --- a/src/southbridge/intel/bd82x6x/reset.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <reset.h> - -void do_soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void do_hard_reset(void) -{ - outb(0x06, 0xcf9); -} diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 0f75537247..47a714b323 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -1,5 +1,10 @@ config SOUTHBRIDGE_INTEL_COMMON def_bool n + select SOUTHBRIDGE_INTEL_COMMON_RESET + +config SOUTHBRIDGE_INTEL_COMMON_RESET + bool + select HAVE_CF9_RESET config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 961b71bbd8..249d2496ef 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -16,6 +16,12 @@ # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. subdirs-y += firmware +verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) romstage-y += pmbase.c diff --git a/src/soc/intel/broadwell/include/soc/reset.h b/src/southbridge/intel/common/reset.c index 4edb598ae2..5a23afa38e 100644 --- a/src/soc/intel/broadwell/include/soc/reset.h +++ b/src/southbridge/intel/common/reset.c @@ -1,8 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -13,9 +11,10 @@ * GNU General Public License for more details. */ -#ifndef _BROADWELL_RESET_H_ -#define _BROADWELL_RESET_H_ - -void reset_system(void); +#include <cf9_reset.h> +#include <reset.h> -#endif +void do_board_reset(void) +{ + system_reset(); +} diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index cf693f6812..52810ab6c1 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_HARD_RESET select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc index 93253e94ef..07192e2a1b 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc +++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc @@ -23,7 +23,6 @@ ramstage-y += sata.c ramstage-y += me.c ramstage-y += me_8.x.c ramstage-y += me_status.c -ramstage-y += reset.c ramstage-y += watchdog.c ramstage-$(CONFIG_ELOG) += elog.c @@ -37,7 +36,6 @@ romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c early_init romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c smm-$(CONFIG_USBDEBUG) += usb_debug.c -romstage-y += reset.c romstage-y += early_spi.c CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c deleted file mode 100644 index b1468da64b..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <reset.h> - -void do_soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void do_hard_reset(void) -{ - outb(0x06, 0xcf9); -} diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig index 9dd62ed742..0bc9586cb2 100644 --- a/src/southbridge/intel/fsp_i89xx/Kconfig +++ b/src/southbridge/intel/fsp_i89xx/Kconfig @@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_HARD_RESET select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM diff --git a/src/southbridge/intel/fsp_i89xx/Makefile.inc b/src/southbridge/intel/fsp_i89xx/Makefile.inc index d8eb06789f..3d2ab69ee4 100644 --- a/src/southbridge/intel/fsp_i89xx/Makefile.inc +++ b/src/southbridge/intel/fsp_i89xx/Makefile.inc @@ -22,7 +22,6 @@ ramstage-y += sata.c ramstage-y += me.c ramstage-y += me_8.x.c ramstage-y += me_status.c -ramstage-y += reset.c ramstage-y += watchdog.c ramstage-$(CONFIG_ELOG) += elog.c @@ -35,7 +34,6 @@ romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c early_init romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c smm-$(CONFIG_USBDEBUG) += usb_debug.c -romstage-y += reset.c romstage-y += early_spi.c romstage-y += romstage.c diff --git a/src/southbridge/intel/fsp_i89xx/reset.c b/src/southbridge/intel/fsp_i89xx/reset.c deleted file mode 100644 index b1468da64b..0000000000 --- a/src/southbridge/intel/fsp_i89xx/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <reset.h> - -void do_soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void do_hard_reset(void) -{ - outb(0x06, 0xcf9); -} diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index afe00bd6aa..268ea668ba 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -31,7 +31,7 @@ #include <console/usb.h> #include <halt.h> #include <program_loading.h> -#include <reset.h> +#include <cf9_reset.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <northbridge/intel/fsp_sandybridge/northbridge.h> #include <northbridge/intel/fsp_sandybridge/raminit.h> @@ -42,12 +42,6 @@ #include "pch.h" #include "romstage.h" -static inline void reset_system(void) -{ - hard_reset(); - halt(); -} - static void pch_enable_lpc(void) { pci_devfn_t dev = PCH_LPC_DEV; @@ -202,7 +196,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { cbmem_was_initted = !cbmem_recovery(0); if (cbmem_was_initted) { - reset_system(); + system_reset(); } /* Save the HOB pointer in CBMEM to be used in ramstage. */ diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig index 3cd5861e00..c15c48d445 100644 --- a/src/southbridge/intel/fsp_rangeley/Kconfig +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_HARD_RESET select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc index 6ab18a7a9d..ace227c92e 100644 --- a/src/southbridge/intel/fsp_rangeley/Makefile.inc +++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc @@ -19,13 +19,12 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y) ramstage-y += soc.c ramstage-y += lpc.c ramstage-y += sata.c -ramstage-y += reset.c ramstage-y += watchdog.c ramstage-y += spi.c ramstage-y += smbus.c ramstage-y += acpi.c -romstage-y += early_usb.c early_smbus.c gpio.c reset.c early_spi.c early_init.c +romstage-y += early_usb.c early_smbus.c gpio.c early_spi.c early_init.c romstage-y += romstage.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/fsp_rangeley/reset.c b/src/southbridge/intel/fsp_rangeley/reset.c deleted file mode 100644 index 10b82ff4e5..0000000000 --- a/src/southbridge/intel/fsp_rangeley/reset.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2013 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <reset.h> - -void do_soft_reset(void) -{ - hard_reset(); -} - -void do_hard_reset(void) -{ - outb(0x02, 0xcf9); - outb(0x06, 0xcf9); -} diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 19e890f58b..827f6bb0f6 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -18,7 +18,6 @@ config SOUTHBRIDGE_INTEL_I82801DX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_HARD_RESET select HAVE_SMI_HANDLER select HAVE_USBDEBUG select SOUTHBRIDGE_INTEL_COMMON diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index c51488390d..7d87995259 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -24,8 +24,6 @@ ramstage-y += lpc.c ramstage-y += usb.c ramstage-y += usb2.c -ramstage-y += reset.c - ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/southbridge/intel/i82801dx/reset.c b/src/southbridge/intel/i82801dx/reset.c deleted file mode 100644 index 1839ad6f9a..0000000000 --- a/src/southbridge/intel/i82801dx/reset.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2004 Ronald G. Minnich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <reset.h> - -void do_hard_reset(void) -{ - /* Try rebooting through port 0xcf9 */ - outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); -} diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index fbae6452eb..28d42ffbe9 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -18,7 +18,6 @@ config SOUTHBRIDGE_INTEL_I82801GX select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON select IOAPIC - select HAVE_HARD_RESET select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index bb68d933b6..0f651e0725 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -30,7 +30,6 @@ ramstage-y += usb_ehci.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -ramstage-y += reset.c ramstage-y += watchdog.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c diff --git a/src/southbridge/intel/i82801gx/reset.c b/src/southbridge/intel/i82801gx/reset.c deleted file mode 100644 index e18f3e8ddc..0000000000 --- a/src/southbridge/intel/i82801gx/reset.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <reset.h> - -void do_soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -#if 0 -void do_hard_reset(void) -{ - /* Try rebooting through port 0xcf9. */ - outb((1 << 2) | (1 << 1), 0xcf9); -} -#endif - -void do_hard_reset(void) -{ - outb(0x02, 0xcf9); - outb(0x06, 0xcf9); -} diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 0c5aabfc40..571778a020 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -21,7 +21,6 @@ config SOUTHBRIDGE_INTEL_I82801IX select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select IOAPIC select HAVE_USBDEBUG - select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 32d8221213..3cc7da5ead 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -29,7 +29,6 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -ramstage-y += ../i82801gx/reset.c ramstage-y += ../i82801gx/watchdog.c ifneq ($(CONFIG_SMM_TSEG),y) diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index cb5b12fcd0..e56d692fb3 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -22,7 +22,6 @@ config SOUTHBRIDGE_INTEL_I82801JX select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select IOAPIC select HAVE_USBDEBUG - select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index d6a3a7ddf5..1053659d68 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -29,7 +29,6 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c -ramstage-y += ../i82801gx/reset.c ramstage-y += ../i82801gx/watchdog.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 5b085b7e1d..fe6526dc88 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -22,7 +22,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select IOAPIC - select HAVE_HARD_RESET select HAVE_USBDEBUG select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 7714f9578a..906652d565 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c ramstage-y += ../bd82x6x/me_status.c -ramstage-y += ../bd82x6x/reset.c ramstage-y += ../bd82x6x/watchdog.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c @@ -41,7 +40,6 @@ ramstage-y += smi.c smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c -romstage-y += ../bd82x6x/reset.c romstage-y += ../bd82x6x/early_rcba.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index dc25b850d8..32485c5c89 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -25,7 +25,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select IOAPIC - select HAVE_HARD_RESET select HAVE_USBDEBUG_OPTIONS select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 7ea0d8bccc..db3454691f 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -36,7 +36,6 @@ endif ramstage-y += rcba.c ramstage-y += me_status.c -ramstage-y += reset.c ramstage-y += watchdog.c ramstage-y += acpi.c @@ -47,7 +46,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c -romstage-y += reset.c early_spi.c rcba.c pmutil.c +romstage-y += early_spi.c rcba.c pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c @@ -55,6 +54,4 @@ ramstage-y += lp_gpio.c smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c endif -postcar-y += reset.c - endif diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c deleted file mode 100644 index 7faadb62df..0000000000 --- a/src/southbridge/intel/lynxpoint/reset.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <reset.h> - -void do_soft_reset(void) -{ - outb(0x04, 0xcf9); -} - -void do_hard_reset(void) -{ - outb(0x06, 0xcf9); -} |