10 files changed, 2 insertions, 65 deletions
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c
index bd204cdb64..893956b259 100644
--- a/src/soc/intel/alderlake/bootblock/pch.c
+++ b/src/soc/intel/alderlake/bootblock/pch.c
@@ -9,7 +9,6 @@
 #include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
-#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -39,11 +38,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN         0x01
 #define PCR_PSFX_T0_SHDW_PCIEN              0x1C
 
-#define PCR_DMI_ACPIBA                      0x27B4
-#define PCR_DMI_ACPIBDID                    0x27B8
-#define PCR_DMI_PMBASEA                     0x27AC
-#define PCR_DMI_PMBASEC                     0x27B0
-
 static void soc_config_pwrmbase(void)
 {
 	/*
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index a4f47c990b..7651cdfe42 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -4,7 +4,6 @@
 #include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
-#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/gspi.h>
@@ -34,11 +33,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 
-#define PCR_DMI_ACPIBA		0x27B4
-#define PCR_DMI_ACPIBDID	0x27B8
-#define PCR_DMI_PMBASEA		0x27AC
-#define PCR_DMI_PMBASEC		0x27B0
-
 static uint32_t get_pmc_reg_base(void)
 {
 	if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
diff --git a/src/soc/intel/common/block/include/intelblocks/dmi.h b/src/soc/intel/common/block/include/intelblocks/dmi.h
deleted file mode 100644
index 8b12602434..0000000000
--- a/src/soc/intel/common/block/include/intelblocks/dmi.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef SOC_INTEL_COMMON_BLOCK_DMI_H
-#define SOC_INTEL_COMMON_BLOCK_DMI_H
-
-#include <types.h>
-
-#define PCR_DMI_DMICTL		0x2234
-#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
-
-#define PCR_DMI_GCS		0x274C
-#define  PCR_DMI_GCS_BILD	(1 << 0)
-
-/*
- * Takes base, size and destination ID and configures the GPMR
- * for accessing the region.
- */
-enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id);
-
-#endif /* SOC_INTEL_COMMON_BLOCK_DMI_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index 43a30010d3..3590852034 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -25,13 +25,6 @@
 #define LPC_IOE_COMA_EN			(1 << 0)
 #define LPC_NUM_GENERIC_IO_RANGES	4
 
-#define PCR_DMI_LPCLGIR1		0x2730
-
-#define PCR_DMI_LPCGMR			0x2740
-
-#define PCR_DMI_LPCIOD			0x2770
-#define PCR_DMI_LPCIOE			0x2774
-
 /* LPC PCR configuration */
 #define PCR_LPC_PRC			0x341c
 #define PCR_LPC_CCE_EN			0xf
diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c
index 09b78bea3e..306908f27d 100644
--- a/src/soc/intel/elkhartlake/bootblock/pch.c
+++ b/src/soc/intel/elkhartlake/bootblock/pch.c
@@ -5,7 +5,6 @@
 #include <device/device.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
-#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -32,11 +31,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 
-#define PCR_DMI_ACPIBA		0x27B4
-#define PCR_DMI_ACPIBDID	0x27B8
-#define PCR_DMI_PMBASEA		0x27AC
-#define PCR_DMI_PMBASEC		0x27B0
-
 static void soc_config_pwrmbase(void)
 {
 	/*
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index 7694a104e1..7ab7ed9a25 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -3,7 +3,6 @@
 #include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
-#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -28,11 +27,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 
-#define PCR_DMI_ACPIBA		0x27B4
-#define PCR_DMI_ACPIBDID	0x27B8
-#define PCR_DMI_PMBASEA		0x27AC
-#define PCR_DMI_PMBASEC		0x27B0
-
 static void soc_config_pwrmbase(void)
 {
 	/*
diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c
index a3c338e127..4de63f2eb5 100644
--- a/src/soc/intel/jasperlake/bootblock/pch.c
+++ b/src/soc/intel/jasperlake/bootblock/pch.c
@@ -5,7 +5,6 @@
 #include <device/mmio.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
-#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -32,11 +31,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 
-#define PCR_DMI_ACPIBA		0x27B4
-#define PCR_DMI_ACPIBDID	0x27B8
-#define PCR_DMI_PMBASEA		0x27AC
-#define PCR_DMI_PMBASEC		0x27B0
-
 static void soc_config_pwrmbase(void)
 {
 	/*
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index ec60cabbea..cc2d384e2e 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -2,7 +2,6 @@
 #include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci_def.h>
-#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/itss.h>
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 73514926ec..9758dba253 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -11,7 +11,6 @@
 #include <device/device.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
-#include <intelblocks/dmi.h>
 #include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/lpc_lib.h>
@@ -42,11 +41,6 @@
 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
 #define PCR_PSFX_T0_SHDW_PCIEN	0x1C
 
-#define PCR_DMI_ACPIBA		0x27B4
-#define PCR_DMI_ACPIBDID	0x27B8
-#define PCR_DMI_PMBASEA		0x27AC
-#define PCR_DMI_PMBASEC		0x27B0
-
 static void soc_config_pwrmbase(void)
 {
 	/*
diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c
index d2496b12fe..a8f47d3378 100644
--- a/src/soc/intel/xeon_sp/pch.c
+++ b/src/soc/intel/xeon_sp/pch.c
@@ -3,7 +3,6 @@
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
-#include <intelblocks/dmi.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/p2sb.h>
@@ -14,6 +13,8 @@
 
 #define PCR_DMI_ACPIBA		0x27B4
 #define PCR_DMI_ACPIBDID	0x27B8
+#define PCR_DMI_DMICTL		0x2234
+#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
 #define PCR_DMI_PMBASEA		0x27AC
 #define PCR_DMI_PMBASEC		0x27B0