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* nb/intel/sandybridge/raminit: fix regression "always use mrccache"4.44.4Patrick Rudolph2016-04-291-7/+14
| | | | | | | | | | | | | | | | | | | Fix regression introduced by: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Don't run channel_test on S3 resume as it overrides memory that might be in use. Fixes MCE events reported by the GNU/Linux kernel that low memory has been modified. Reset on failed s3 resume. Change-Id: Ibadea286619c7906225f86a93aaa0b4caf26cabe Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* siemens/mc_bdx1: Add new mainboard.Werner Zeh2016-04-2915-0/+814
| | | | | | | | | | | | | | | | | | | Add new mainboard for MC BDX1 board which is based on Intel Camelback Mountain. This mainboard is an industry type board and has several Ethernet interfaces among with two USB3.0 connectors. It uses 24V DC power supply and has its own form factor which does not match any standard. This commit adds the new mainboard and prepares the Kconfig environment so that this board can be selected and generated. Although the generated image can boot into Linux and DOS, not all functions are implemented yet. Forthcoming commits will add more functionality. Change-Id: I29011cfd3b0d13bcf163223f657e02f69978e39a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14516 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com>
* nb/amd/mct_ddr3: Restart system on training failure instead of using die()Timothy Pearson2016-04-281-1/+4
| | | | | | | | | | | | | | DIMM training can sporadically fail due to external influences or various errata. In these cases, restarting to retry training is a more appropriate response than halting the system and requiring manual intervention. Change-Id: Id49f7419f56e0640a84448cc06ecbaf62bed145e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14529 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Add board URLs for the RISC-V boardsJonathan Neuschäfer2016-04-282-0/+2
| | | | | | | | Change-Id: Ifdf40986c2407d8c5b0097654b42e056f4498d39 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14518 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Fix "Spike RISCV" board nameJonathan Neuschäfer2016-04-281-1/+1
| | | | | | | | Change-Id: If0f835e69862a78433e7c1a34efa4706cc27b214 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/14517 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* fsp_baytrail: Fix missing "$" when using Kconfig switchWerner Zeh2016-04-281-1/+1
| | | | | | | | | | | | | To include gfx.c in ramstage, there is a Kconfig option (FSP_BAYTRAIL_GFX_INIT) which can be activated on demand. Unfortunately, the "$"-character is missing so that this switch is never active. Change-Id: I0c3c562b3caca53ac6510c2c5dc30e7f606f5ad0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14532 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* drivers/intel/i210: Use uint8_t and friends instead of u8Werner Zeh2016-04-283-35/+40
| | | | | | | | | | | Switch all types to uint8_t and the like instead of u8. Change-Id: Ia12c4ee9e21e2d3166c2f895c819357fa2ed9a94 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14515 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mc_tcu3: Switch to hwilib instead of own hwinfo implementationWerner Zeh2016-04-289-377/+120
| | | | | | | | | | | | Use hwilib in vendorcode/siemens/hwilib to get fields from hwinfo instead of having mainboard specific hwinfo code. This patch does not change the functional behavior in any way. Change-Id: Idb226a82a08b1b753f654c5cde106236e72f33c3 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14506 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* vendorcode/siemens: Add hwilib for Siemens specific info structWerner Zeh2016-04-286-0/+451
| | | | | | | | | | | | | | Add a library which unifies access to Siemens specific hardware information data. This library is meant to be used with Siemens platforms and can be selected in Kconfig. The needed source of information has to be present in cbfs. This lib can be used in romstage and ramstage. Change-Id: I2c6e003b0c123b4cf6a84906c2b133b8c38c8b1a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14505 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS buildsLance Zhao2016-04-286-0/+110
| | | | | | | | | | | Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: Add GPIO devicesZhao, Lijian2016-04-283-0/+148
| | | | | | | | | | | | | | Add GPIO controller in ACPI device description. GPIO controller driver is probed in kernel and all the pins in the banks are showing respective values. Change-Id: I0512cfec872113b15fd204ec3b95efeac87f694a Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/14478 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: Add cache for BIOS ROMAndrey Petrov2016-04-282-0/+22
| | | | | | | | | | | Enable caching of BIOS region with variable MTRR. This is most useful if enabled early such as in bootblock. Change-Id: I39f33ca43f06fce26d1d48e706c97f097e3c10f1 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14480 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* soc/intel/apollolake: Enable LPC bus interfaceAndrey Petrov2016-04-285-1/+123
| | | | | | | | | | | | | This adds early LPC setup in bootblock (for Chrome EC) as well as late (ramstage) IO decode/sirq enable. Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14469 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: Enable RAM cache for cbmem region in ramstageAndrey Petrov2016-04-281-0/+13
| | | | | | | | | | | Use postcar infrastructure to enable caching of area where ramstage runs. Change-Id: I3f2f6e82f3b9060c7350ddff754cd3dbcf457671 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14095 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: Fix northbridge _crs scopeZhao, Lijian2016-04-281-83/+84
| | | | | | | | | | | Move _CRS scope from MCHC device only to whole pci root bus. Otherwise ACPI will not able to assign resource to devices other than MCHC. Change-Id: Iaa294c63e03a4fc6644f1be5d69ab3de077e6cc3 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/14477 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mainboard/amenia: Enable Chrome EC Interface/KeyboardDivya Sasidharan2016-04-288-0/+158
| | | | | | | | | | | | Enabled LPC channel between host and EC. Superio.asl will enable proper probing of onboard keyboard. Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/14468 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: Configure a GPIO for TPM in bootblockAndrey Petrov2016-04-283-35/+15
| | | | | | | | | | | | One of devices connected to FAST SPI bus is TPM. SoC uses dedicated line for chip select for TPM function. If TPM is used, that line needs to be configured to a specific native funciton. Change-Id: Ib5bf4c759adf9656f7b34540d4fc924945d27a97 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14467 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: Avoid marking 0xe0000-0xfffff region usableAndrey Petrov2016-04-281-4/+6
| | | | | | | | | | | coreboot writes RDSP at 0xf0000. Since depthcharge wipes usable memory regions before starting, kernel can't find RDSP. Change-Id: I584bd5d24248cf38f46342615cf3b0252a821b2a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: Actually include ACPI PCI IRQ definitionsAndrey Petrov2016-04-282-0/+4
| | | | | | | | | | | Without ACPI PCI IRQ definitions kernel is left only with informaiton available in PCI config space, which is not sufficient. Change-Id: I3854781049851b5aa5b2dbf3257ece2fee76c3e2 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* payloads: Add a stable version of Memtest86+ for reproducibilityMartin Roth2016-04-273-3/+28
| | | | | | | | | | | | | | | | Memtest86+ was pulling origin/master which will change over time. This adds a commit-id as a stable version to allow it to be reproducible. The other secondary payloads, coreinfo and nvramcui, do not need this because they are part of the coreboot repo and not fetched from an external source. Change-Id: I20c516010f76cf03342bd8883d0ee7ac5f8bc7e4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14520 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Memtest86Plus/Makefile: Update to common payload makefile formatMartin Roth2016-04-271-7/+17
| | | | | | | | | | | | | | | | | This series of patches attempts to update all of the external payload makefiles to be as similar as possible. - Add .git to the git repo URL to show that it's a git repo. - Use the common checkout, fetch, and clone ($(project dir)) targets - Add TAG-y and NAME-y variables - just with origin/master for now. Stable will be added shortly. - Make sure all phony targets are in .PHONY Change-Id: If83c100841d5f91a9fab7ac44ba20ec2271c0594 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14152 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* board_status/to-wiki: Fix background color of very recent test resultsTimothy Pearson2016-04-261-0/+3
| | | | | | | | | | | | | Test results under 16 days old display with an incorrect background color due to the leading zero not being preset in the associated HTML color code. Add the leading zero where needed to generate a valid HTML color code. Change-Id: I0dfe29ec1afc409a4908073922ac31a4091f0f1f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14514 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* coreinfo: Update MakefileMartin Roth2016-04-261-2/+2
| | | | | | | | | | | | | | - Get the absolute pathname for LIBPAYLOAD_PATH - Update distclean: --correctly remove .config and .config.old - *.config doesn't match .config -- remove obsolete files from cleanup Change-Id: I6aa51b4ac2b392f786aeb12647be5073e6d02df5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14485 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* nvramcui: Reformat nvramcui.cMartin Roth2016-04-261-51/+67
| | | | | | | | Change-Id: I89dca25d93a4c94cc51f313397e49ba763948450 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14484 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* nvramcui: Remove unnecessary header filesMartin Roth2016-04-261-3/+0
| | | | | | | | Change-Id: If845729bc34df646a5628ac2a35acc737fd4701d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14483 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* mainboard/kgpe-d16|kcma-d8: Update memory test to include second PRNG stageTimothy Pearson2016-04-262-14/+110
| | | | | | | | | | | | | | | | The existing memory test routine was insufficient to detect certain types of bus instability related to multiple incompatible RDIMMs on one channel. Add a PRNG second stage test to the memory test routine. This second stage test reliably detects faults in memory setup for RDIMM configurations that also fail under the proprietary BIOS. Change-Id: I44721447ce4c2b728d4a8f328ad1a3eb8f324d3d Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14502 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
* nb/amd/mct_ddr3: Report correct DIMM in MRS setup routinesTimothy Pearson2016-04-261-3/+3
| | | | | | | | | | | | | The wrong DIMM number was used in the initial non-target MRS setup routines. This had no functional impact other than to print the wrong DIMM number in the DDR3 verbose debug output. Change-Id: I480118ed00e1786a06e641a56f0fb19cd87f92eb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14501 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
* nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setupTimothy Pearson2016-04-261-17/+72
| | | | | | | | | | | | | | | | | | The existing RDIMM RC control word send routines were a hodgepodge of various AGESA chunks with different ways of handling the same task. Unify the control word chip select setup, use precise timing routines on Family 15h, fix a couple of incorrect masks, and add additional debugging statements. It is believed that this patch is cosmetic and does not significantly alter existing functionality. Change-Id: Ie4ec7b6a7be7fce09e89f9eec146cc98b15b6160 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14500 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
* ensure correct byte ordering for cbfs segment listGeorge Trudeau2016-04-252-45/+60
| | | | | | | | | | | | | | | | | Decode each cbfs_payload_segment into native byte order during segments iteration. Note : List ordering has been changed, segments are now always inserted at the end. cbfs_serialized.h PAYLOAD_SEGMENT definitions have been changed to their standard order (big-endian). Change-Id: Icb3c6a7da2d253685a3bc157bc7f5a51183c9652 Signed-off-by: George Trudeau <george.trudeau@usherbrooke.ca> Reviewed-on: https://review.coreboot.org/14294 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK changeTimothy Pearson2016-04-252-3/+3
| | | | | | | | | | | | | | | | When more than one DIMM is installed on a DCT, only the first DIMM delay values are scaled to the new memory clock frequency after a memory clock change during write leveling. Store the previous memory clock of each DIMM during write leveling to ensure that every DIMM has its delay values rescaled. Change-Id: I56e816d3d3256925598219d92783246f5f4ab567 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14479 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
* board_status/to-wiki: Indicate age of test results by background colorTimothy Pearson2016-04-251-1/+17
| | | | | | | | | | | | | | | | | | | | A major issue with the board-status Wiki page is that it shows all test results equally regardless of age. As a test result ages it becomes more likely that the board no longer works peroperly under coreboot due to code churn. Visually indicate board-test status "at a glance" by smoothly fading the background color of the test result from green to yellow as the test result ages. This patch sets the full yellow transition to 255 days after test for programming convenience, however the number of days required to fully "stale" a test result could be modified relatively easily. Change-Id: I5a076a6cc17d53fda8e4681e38074fc1f46c0e12 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14457 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
* payloads/Makefile.inc: Add phony targetsMartin Roth2016-04-251-2/+2
| | | | | | | | | | | | | Add 'nvramcui' target to make it easier to build and test. Put both nvramcui & coreinfo targets into .PHONY because they both exist as directories. Change-Id: I9cf76785e69f3c8e47fe92f1b1648fd0f7a63c3e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14481 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Reject duplicate results in board-status.Huimin Zhang2016-04-241-0/+15
| | | | | | | | | | | This is in response to issue #28: board-status should reject duplicate uploads. Change-Id: Iff99be154b35e8c0f9f05f9470d1c2dcff8510b8 Signed-off-by: Huimin Zhang <thehobn@gmail.com> Reviewed-on: https://review.coreboot.org/14187 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* fmaptool: Make sure strings are not destroyed on hdestroy()Stefan Reinauer2016-04-221-1/+14
| | | | | | | | | | | | | On Mac OS X hdestroy seems to overwrite node->name. Hence duplicate the string before stuffing it into the hash search table. Change-Id: Ieac2025f5c960cdb8d509dde7e92ba0dd32644b0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14443 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* drivers/ricoh: Fully switch to src/drivers/[X]/[Y]/ schemeStefan Reinauer2016-04-221-1/+0
| | | | | | | | | | The previous commit removed Kconfig, but not Makefile.inc Change-Id: If46a0a3e253eea9d286d8ab3b1a6ab67ef678ee4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14419 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* soc/intel/quark: Fix MTRR readsLee Leahy2016-04-221-1/+0
| | | | | | | | | | | | | Remove offset override improperly added in the "Disable the ROM shadow" patch TEST=Build and run on Galileo Gen2 Change-Id: I32fb2da48e3769d59a49619539053f9afdf63b04 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14450 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* soc/intel/quark: Fix uninitialized variable d_variantLee Leahy2016-04-221-0/+1
| | | | | | | | | | | | | | Initialize the d_variant variable. Found-by: CID 1353356 Uninitialized variable TEST=Build and run on Galileo Gen2 Change-Id: I26fba4e77f91d53b6ff9028669aa0186d3174639 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14338 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"Timothy Pearson2016-04-223-27/+27
| | | | | | | | | | | | | | | | | | After substantial testing it has been determined that it is neither required nor safe to disable the DRAM MCA during initial startup. This (mostly) reverts commit c094d9961144871c472698c41ce634e58abb6a32. The minor debugging enhancements from that commit were left in place. Tested-On: ASUS KGPE-D16 Config-CPU: 1x Opteron 6262HE Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1 Config-RAM: 1x Kingston 9965516-483.A00LF Change-Id: I58fcc296b8c45ecaedf540951c365e4ce52baaf5 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14446 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
* nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency changeTimothy Pearson2016-04-221-1/+7
| | | | | | | | | Change-Id: I5056cf885b7063a97c095bfaaf01dd8da777a425 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14447 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
* nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMsTimothy Pearson2016-04-221-44/+39
| | | | | | | | | | | | | | | | | | | | | | | | Certain RDIMMs have inherently large write levelling delays, in some cases exceeding 1.5 MEMCLK. When these DIMMs are utilized, the phase recovery system requires special handling due to the resultant offset exceeding the phase recovery reporting capabilities. Fix an old error where delays > 1.5 MEMCLK were not being programmed (gross delay high bit was not in set range), and restore special delay handling for delays greater than 1.5 MEMCLK. Also enhance debugging for x4 DIMMs around the affected code. Tested-On: ASUS KGPE-D16 Config-CPU: 1x Opteron 6262HE Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1 Change-Id: I0fb5454c4d5a9f308cc735597607f095fe9188db Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14441 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* nb/amd/mct_ddr3: Run fence training on each node after memory clock changeTimothy Pearson2016-04-221-2/+2
| | | | | | | | | | | | | | | | | | | The BKDG requires phy fences to be re-trained after a memory clock change. Memory training on the ASUS KGPE-D16 and KCMA-D8 somehow "mostly" worked -- without actually following this requirement -- ! Fix the single typo that caused several weeks of delay in putting servers with Kingston RAM (and others) into production... Tested-On: ASUS KGPE-D16 Config-CPU: 1x Opteron 6262HE Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1 Change-Id: I197e6728d2b0ac8c1535740599459d080b17af33 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14445 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/intel/apollolake: Flush L1D to L2 only if loaded segment is in CARFurquan Shaikh2016-04-221-4/+21
| | | | | | | | | | | | In program_segment_loaded, flush L1D to L2 only if the address of the loaded segment lies in the CAR region. Add an assert to ensure that the loaded segment does not cross CAR boundaries. Change-Id: Ie43e99299ed82f01518c8a1c1fd2bc64747d0c7b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14449 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* intel/i82801ax: Fix IDE setup console logPatrick Georgi2016-04-221-2/+2
| | | | | | | | | | | | | | Fixes two issues: 1. In (the unlikely) case that dev->chip_info is NULL, the output was depending on an unknown value near the start of the address space. 2. Output for the secondary interface actually printed the primary interface's configuration. Change-Id: Id0f499a85e6e2410b4efd63baf7fffb2fcaa3103 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14361 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* lint/checkpatch.pl: escape \{ in perl regex to fix warningsAlexander Couzens2016-04-221-5/+5
| | | | | | | | | | | | | | | Fix warnings: Unescaped left brace in regex is deprecated, passed through in regex; marked by <-- HERE in m/\#\s*define.*do\s{ <-- HERE / at util/lint/checkpatch.pl line 3261. marked by <-- HERE in m/\(.*\){ <-- HERE / at util/lint/checkpatch.pl line 3750. marked by <-- HERE in m/do{ <-- HERE / at util/lint/checkpatch.pl line 3751. marked by <-- HERE in m/^\({ <-- HERE / at util/lint/checkpatch.pl line 4194. Change-Id: If0c1f07a16df9e6cd1c1393a31af8b8ea6a66b01 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/14310 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/lint: Find unsigned variables with no length specifiedMartin Roth2016-04-211-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | The coding guidelines say that all objects should have fully qualified types (unsigned int instead of unsigned). This script finds violations of that rule. Steps for the filter: 1) Find all lines in the coreboot tree that have the word 'unsigned' followed by a space. 2) Exclude directories that aren't in the include list or are specifically excluded. 3) Exclude files that aren't specifically included. 4) Filter out legimitate uses 'unsigned int' or 'unsigned long' for example. 5) Filter out lines that begin with '/*' or '*' Change-Id: I46213c6a168e6aafa29a50af814bf7e0fcd32eb6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14269 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: time: split time.h from libpayload.hStef van Os2016-04-212-14/+51
| | | | | | | | | | | | | Move time functions and prototypes from libpayload.h to time.h. In a similar manner to other c libary headers, this change makes porting existing applications to libpayload easier. Change-Id: I71e27c6dddde6e77e0e9b4d7be7cd5298e03a648 Signed-off-by: Stef van Os <stef.van.os@prodrive-technologies.com> Reviewed-on: https://review.coreboot.org/14437 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* lint: Add check for amd & apple mainboard license headersMartin Roth2016-04-211-2/+2
| | | | | | | | Change-Id: Idda4b7179e3e7b3f5b70be810b428b0651c1cd67 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14427 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* coreinfo: Build libpayload in coreinfo directoryIru Cai2016-04-211-5/+6
| | | | | | | | | | | | When building libpayload, make the build directory and .config outside libpayload source directory so it'll not pollute the libpayload source and cause conflicts with other builds. Change-Id: Idcfbc7dbe4d52a3559229d8450c3efaafd33b93b Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/14389 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* lib: add common write_tables() implementationAaron Durbin2016-04-218-253/+50
| | | | | | | | | | | | | | In order to de-duplicate common patterns implement one write_tables() function. The new write_tables() replaces all the architecture-specific ones that were largely copied. The callbacks are put in place to handle any per-architecture requirements. Change-Id: Id3d7abdce5b30f5557ccfe1dacff3c58c59f5e2b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14436 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* lib/coreboot_table: add architecture hooks for adding tablesAaron Durbin2016-04-218-17/+54
| | | | | | | | | | | | Add a architecture specific function, arch_write_tables(), that allows an architecture to add its required tables for booting. This callback helps write_tables() to be de-duplicated. Change-Id: I805c2f166b1e75942ad28b6e7e1982d64d2d5498 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14435 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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