From 349e08535a7666cabe52ebc331e3bce5468b786b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 9 Apr 2017 20:48:37 +0200 Subject: sb/intel/i82801jx: Add correct PCI ids and change names Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/19249 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/southbridge/intel/i82801jx/Kconfig | 2 +- src/southbridge/intel/i82801jx/Makefile.inc | 4 +- src/southbridge/intel/i82801jx/acpi/audio.asl | 2 +- src/southbridge/intel/i82801jx/acpi/ich10.asl | 203 ++++++++++++++++++++++ src/southbridge/intel/i82801jx/acpi/ich9.asl | 203 ---------------------- src/southbridge/intel/i82801jx/acpi/lpc.asl | 4 +- src/southbridge/intel/i82801jx/acpi/pci.asl | 2 +- src/southbridge/intel/i82801jx/acpi/usb.asl | 2 +- src/southbridge/intel/i82801jx/bootblock.c | 5 + src/southbridge/intel/i82801jx/chip.h | 8 +- src/southbridge/intel/i82801jx/dmi_setup.c | 10 +- src/southbridge/intel/i82801jx/early_init.c | 4 +- src/southbridge/intel/i82801jx/early_smbus.c | 7 +- src/southbridge/intel/i82801jx/hdaudio.c | 15 +- src/southbridge/intel/i82801jx/i82801ix.c | 235 -------------------------- src/southbridge/intel/i82801jx/i82801ix.h | 232 ------------------------- src/southbridge/intel/i82801jx/i82801jx.c | 235 ++++++++++++++++++++++++++ src/southbridge/intel/i82801jx/i82801jx.h | 234 +++++++++++++++++++++++++ src/southbridge/intel/i82801jx/lpc.c | 58 +++---- src/southbridge/intel/i82801jx/pci.c | 7 +- src/southbridge/intel/i82801jx/pcie.c | 30 ++-- src/southbridge/intel/i82801jx/sata.c | 18 +- src/southbridge/intel/i82801jx/smbus.c | 7 +- src/southbridge/intel/i82801jx/smbus.h | 2 +- src/southbridge/intel/i82801jx/smi.c | 4 +- src/southbridge/intel/i82801jx/smihandler.c | 2 +- src/southbridge/intel/i82801jx/thermal.c | 12 +- src/southbridge/intel/i82801jx/usb_ehci.c | 8 +- 28 files changed, 793 insertions(+), 762 deletions(-) create mode 100644 src/southbridge/intel/i82801jx/acpi/ich10.asl delete mode 100644 src/southbridge/intel/i82801jx/acpi/ich9.asl delete mode 100644 src/southbridge/intel/i82801jx/i82801ix.c delete mode 100644 src/southbridge/intel/i82801jx/i82801ix.h create mode 100644 src/southbridge/intel/i82801jx/i82801jx.c create mode 100644 src/southbridge/intel/i82801jx/i82801jx.h (limited to 'src/southbridge/intel/i82801jx') diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 99dd1aaea9..d05e32eb12 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -38,6 +38,6 @@ config HPET_MIN_TICKS config BOOTBLOCK_SOUTHBRIDGE_INIT string - default "southbridge/intel/i82801ix/bootblock.c" + default "southbridge/intel/i82801jx/bootblock.c" endif diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 975a068e69..9121c3d964 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -16,7 +16,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y) -ramstage-y += i82801ix.c +ramstage-y += i82801jx.c ramstage-y += pci.c ramstage-y += lpc.c ramstage-y += pcie.c @@ -36,8 +36,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -romstage-y += early_init.c romstage-y += early_smbus.c -romstage-y += dmi_setup.c endif diff --git a/src/southbridge/intel/i82801jx/acpi/audio.asl b/src/southbridge/intel/i82801jx/acpi/audio.asl index b09f2af34d..afae905079 100644 --- a/src/southbridge/intel/i82801jx/acpi/audio.asl +++ b/src/southbridge/intel/i82801jx/acpi/audio.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -/* Intel i82801I HDA */ +/* Intel i82801L HDA */ // Intel High Definition Audio (Azalia) 0:1b.0 diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl new file mode 100644 index 0000000000..da8b789baa --- /dev/null +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -0,0 +1,203 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Intel 82801Ix support */ + +Scope(\) +{ + // IO-Trap at 0x800. This is the ACPI->SMI communication interface. + + OperationRegion(IO_T, SystemIO, 0x800, 0x10) + Field(IO_T, ByteAcc, NoLock, Preserve) + { + Offset(0x8), + TRP0, 8 // IO-Trap at 0x808 + } + + // ICH10 Power Management Registers, located at PMBASE (0x1f.0 0x40.l) + OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) + Field(PMIO, ByteAcc, NoLock, Preserve) + { + Offset(0x11), + THRO, 1, // force thermal throttling + Offset(0x42), // General Purpose Control + , 1, // skip 1 bit + GPEC, 1, // TCO status + Offset(0x64), + , 9, // skip 9 more bits + SCIS, 1 // TCO DMI status + } + + // FIXME: purposes of the GPIOs (comments) are probably wrong + // ICH10 GPIO IO mapped registers (0x1f.0 reg 0x48.l) + OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) + Field(GPIO, ByteAcc, NoLock, Preserve) + { + Offset(0x00), // GPIO Use Select + GU00, 8, + GU01, 8, + GU02, 8, + GU03, 8, + Offset(0x04), // GPIO IO Select + GIO0, 8, + GIO1, 8, + GIO2, 8, + GIO3, 8, + Offset(0x0c), // GPIO Level + GP00, 1, + GP01, 1, + GP02, 1, + GP03, 1, + GP04, 1, + GP05, 1, + GP06, 1, // GDET + GP07, 1, + GP08, 1, + GP09, 1, // HPMU + GP10, 1, // GPSE + GP11, 1, + GP12, 1, // WLED + GP13, 1, // BLED + GP14, 1, // GLED + GP15, 1, // GDIS + GP16, 1, + GP17, 1, + GP18, 1, // SPCI + GP19, 1, // TSDT + GP20, 1, // SCPU + GP21, 1, + GP22, 1, + GP23, 1, // LANP + GP24, 1, // DKLR + GP25, 1, // WLAN + GP26, 1, // SATA_PWR_EN #0 / SPOF + GP27, 1, // SATA_PWR_EN #1 / SPMU + GP28, 1, + GP29, 1, + GP30, 1, + GP31, 1, + Offset(0x18), // GPIO Blink + GB00, 8, + GB01, 8, + GB02, 8, + GB03, 8, + Offset(0x2c), // GPIO Invert + GIV0, 8, + GIV1, 8, + GIV2, 8, + GIV3, 8, + Offset(0x30), // GPIO Use Select 2 + GU04, 8, + GU05, 8, + GU06, 8, + GU07, 8, + Offset(0x34), // GPIO IO Select 2 + GIO4, 8, + GIO5, 8, + GIO6, 8, + GIO7, 8, + Offset(0x38), // GPIO Level 2 + GP32, 1, + GP33, 1, // CREN + GP34, 1, // CRRS + GP35, 1, + GP36, 1, // STAD + GP37, 1, // PATA_PWR_EN / HDDE + GP38, 1, // Battery / Power (?) / MB00 + GP39, 1, // ?? / MB01 + GL05, 8, + GL06, 8, + GL07, 8 + } + + + // ICH10 Root Complex Register Block. Memory Mapped through RCBA) + OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + Field(RCRB, DWordAcc, Lock, Preserve) + { + Offset(0x0000), // Backbone + Offset(0x1000), // Chipset + Offset(0x3000), // Legacy Configuration Registers + Offset(0x3404), // High Performance Timer Configuration + HPAS, 2, // Address Select + , 5, + HPTE, 1, // Address Enable + Offset(0x3418), // FD (Function Disable) + , 2, // Reserved + SA1D, 1, // SATA disable + SMBD, 1, // SMBUS disable + HDAD, 1, // Azalia disable + , 2, // Reserved + US6D, 1, // UHCI #6 disable + US1D, 1, // UHCI #1 disable + US2D, 1, // UHCI #2 disable + US3D, 1, // UHCI #3 disable + US4D, 1, // UHCI #4 disable + US5D, 1, // UHCI #5 disable + EH2D, 1, // EHCI disable + LPBD, 1, // LPC bridge disable + EH1D, 1, // EHCI disable + Offset(0x341a), // FD Root Ports + RP1D, 1, // Root Port 1 disable + RP2D, 1, // Root Port 2 disable + RP3D, 1, // Root Port 3 disable + RP4D, 1, // Root Port 4 disable + RP5D, 1, // Root Port 5 disable + RP6D, 1, // Root Port 6 disable + , 2, // Reserved + THRD, 1, // Thermal Throttle disable + SA2D, 1, // SATA disable + } + +} + +// 0:1b.0 High Definition Audio (Azalia) +#include "audio.asl" + +// PCI Express Ports +#include "pcie.asl" + +// USB +#include "usb.asl" + +// PCI Bridge +#include "pci.asl" + +// LPC Bridge +#include "lpc.asl" + +// SATA +#include "sata.asl" + +// SMBus +#include "smbus.asl" + +Method (_OSC, 4) +{ + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } +} diff --git a/src/southbridge/intel/i82801jx/acpi/ich9.asl b/src/southbridge/intel/i82801jx/acpi/ich9.asl deleted file mode 100644 index 143ecb1f2d..0000000000 --- a/src/southbridge/intel/i82801jx/acpi/ich9.asl +++ /dev/null @@ -1,203 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Intel 82801Ix support */ - -Scope(\) -{ - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. - - OperationRegion(IO_T, SystemIO, 0x800, 0x10) - Field(IO_T, ByteAcc, NoLock, Preserve) - { - Offset(0x8), - TRP0, 8 // IO-Trap at 0x808 - } - - // ICH9 Power Management Registers, located at PMBASE (0x1f.0 0x40.l) - OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) - Field(PMIO, ByteAcc, NoLock, Preserve) - { - Offset(0x11), - THRO, 1, // force thermal throttling - Offset(0x42), // General Purpose Control - , 1, // skip 1 bit - GPEC, 1, // TCO status - Offset(0x64), - , 9, // skip 9 more bits - SCIS, 1 // TCO DMI status - } - - // FIXME: purposes of the GPIOs (comments) are probably wrong - // ICH9 GPIO IO mapped registers (0x1f.0 reg 0x48.l) - OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) - Field(GPIO, ByteAcc, NoLock, Preserve) - { - Offset(0x00), // GPIO Use Select - GU00, 8, - GU01, 8, - GU02, 8, - GU03, 8, - Offset(0x04), // GPIO IO Select - GIO0, 8, - GIO1, 8, - GIO2, 8, - GIO3, 8, - Offset(0x0c), // GPIO Level - GP00, 1, - GP01, 1, - GP02, 1, - GP03, 1, - GP04, 1, - GP05, 1, - GP06, 1, // GDET - GP07, 1, - GP08, 1, - GP09, 1, // HPMU - GP10, 1, // GPSE - GP11, 1, - GP12, 1, // WLED - GP13, 1, // BLED - GP14, 1, // GLED - GP15, 1, // GDIS - GP16, 1, - GP17, 1, - GP18, 1, // SPCI - GP19, 1, // TSDT - GP20, 1, // SCPU - GP21, 1, - GP22, 1, - GP23, 1, // LANP - GP24, 1, // DKLR - GP25, 1, // WLAN - GP26, 1, // SATA_PWR_EN #0 / SPOF - GP27, 1, // SATA_PWR_EN #1 / SPMU - GP28, 1, - GP29, 1, - GP30, 1, - GP31, 1, - Offset(0x18), // GPIO Blink - GB00, 8, - GB01, 8, - GB02, 8, - GB03, 8, - Offset(0x2c), // GPIO Invert - GIV0, 8, - GIV1, 8, - GIV2, 8, - GIV3, 8, - Offset(0x30), // GPIO Use Select 2 - GU04, 8, - GU05, 8, - GU06, 8, - GU07, 8, - Offset(0x34), // GPIO IO Select 2 - GIO4, 8, - GIO5, 8, - GIO6, 8, - GIO7, 8, - Offset(0x38), // GPIO Level 2 - GP32, 1, - GP33, 1, // CREN - GP34, 1, // CRRS - GP35, 1, - GP36, 1, // STAD - GP37, 1, // PATA_PWR_EN / HDDE - GP38, 1, // Battery / Power (?) / MB00 - GP39, 1, // ?? / MB01 - GL05, 8, - GL06, 8, - GL07, 8 - } - - - // ICH9 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) - Field(RCRB, DWordAcc, Lock, Preserve) - { - Offset(0x0000), // Backbone - Offset(0x1000), // Chipset - Offset(0x3000), // Legacy Configuration Registers - Offset(0x3404), // High Performance Timer Configuration - HPAS, 2, // Address Select - , 5, - HPTE, 1, // Address Enable - Offset(0x3418), // FD (Function Disable) - , 2, // Reserved - SA1D, 1, // SATA disable - SMBD, 1, // SMBUS disable - HDAD, 1, // Azalia disable - , 2, // Reserved - US6D, 1, // UHCI #6 disable - US1D, 1, // UHCI #1 disable - US2D, 1, // UHCI #2 disable - US3D, 1, // UHCI #3 disable - US4D, 1, // UHCI #4 disable - US5D, 1, // UHCI #5 disable - EH2D, 1, // EHCI disable - LPBD, 1, // LPC bridge disable - EH1D, 1, // EHCI disable - Offset(0x341a), // FD Root Ports - RP1D, 1, // Root Port 1 disable - RP2D, 1, // Root Port 2 disable - RP3D, 1, // Root Port 3 disable - RP4D, 1, // Root Port 4 disable - RP5D, 1, // Root Port 5 disable - RP6D, 1, // Root Port 6 disable - , 2, // Reserved - THRD, 1, // Thermal Throttle disable - SA2D, 1, // SATA disable - } - -} - -// 0:1b.0 High Definition Audio (Azalia) -#include "audio.asl" - -// PCI Express Ports -#include "pcie.asl" - -// USB -#include "usb.asl" - -// PCI Bridge -#include "pci.asl" - -// LPC Bridge -#include "lpc.asl" - -// SATA -#include "sata.asl" - -// SMBus -#include "smbus.asl" - -Method (_OSC, 4) -{ - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) - { - /* Let OS control everything */ - Return (Arg3) - } - Else - { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) - Return (Arg3) - } -} diff --git a/src/southbridge/intel/i82801jx/acpi/lpc.asl b/src/southbridge/intel/i82801jx/acpi/lpc.asl index 9d27b0b482..1d9e54e237 100644 --- a/src/southbridge/intel/i82801jx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801jx/acpi/lpc.asl @@ -170,8 +170,8 @@ Device (LPCB) IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap - IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH9 ACPI - IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH9 GPIO + IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH10 ACPI + IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH10 GPIO }) } diff --git a/src/southbridge/intel/i82801jx/acpi/pci.asl b/src/southbridge/intel/i82801jx/acpi/pci.asl index f2988e1951..de164249ee 100644 --- a/src/southbridge/intel/i82801jx/acpi/pci.asl +++ b/src/southbridge/intel/i82801jx/acpi/pci.asl @@ -65,7 +65,7 @@ Device (PCIB) Method (_PRT) { - #include "acpi/ich9_pci_irqs.asl" + #include "acpi/ich10_pci_irqs.asl" } } diff --git a/src/southbridge/intel/i82801jx/acpi/usb.asl b/src/southbridge/intel/i82801jx/acpi/usb.asl index 5fa751a20d..b621263cd4 100644 --- a/src/southbridge/intel/i82801jx/acpi/usb.asl +++ b/src/southbridge/intel/i82801jx/acpi/usb.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -/* Intel i82801I USB support */ +/* Intel i82801J USB support */ // USB Controller 0:1d.0 diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 6252712eba..cc685c4544 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -14,6 +14,7 @@ */ #include +#include "i82801jx.h" static void enable_spi_prefetch(void) { @@ -31,4 +32,8 @@ static void enable_spi_prefetch(void) static void bootblock_southbridge_init(void) { enable_spi_prefetch(); + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA, + (uintptr_t)DEFAULT_RCBA | 1); } diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index 307b751fab..f22748bc05 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -14,15 +14,15 @@ * GNU General Public License for more details. */ -#ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H -#define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H +#ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H +#define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H enum { THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7 }; -struct southbridge_intel_i82801ix_config { +struct southbridge_intel_i82801jx_config { /** * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. @@ -88,4 +88,4 @@ struct southbridge_intel_i82801ix_config { uint8_t pcie_hotplug_map[8]; }; -#endif /* SOUTHBRIDGE_INTEL_I82801IX_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_I82801JX_CHIP_H */ diff --git a/src/southbridge/intel/i82801jx/dmi_setup.c b/src/southbridge/intel/i82801jx/dmi_setup.c index e47586b1ed..83633a4930 100644 --- a/src/southbridge/intel/i82801jx/dmi_setup.c +++ b/src/southbridge/intel/i82801jx/dmi_setup.c @@ -18,7 +18,7 @@ #include #include #include -#include "i82801ix.h" +#include "i82801jx.h" /* VC1 Port Arbitration Table */ static const u8 vc1_pat[] = { @@ -39,7 +39,7 @@ static const u8 vc1_pat[] = { 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; -void i82801ix_dmi_setup(void) +void i82801jx_dmi_setup(void) { int i; u32 reg32; @@ -109,12 +109,12 @@ void i82801ix_dmi_setup(void) } /* Should be called after VC1 has been enabled on both sides. */ -void i82801ix_dmi_poll_vc1(void) +void i82801jx_dmi_poll_vc1(void) { int timeout; timeout = 0x7ffff; - printk(BIOS_DEBUG, "ICH9 waits for VC1 negotiation... "); + printk(BIOS_DEBUG, "ICH10 waits for VC1 negotiation... "); while ((RCBA32(RCBA_V1STS) & (1 << 1)) && --timeout) {} if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); @@ -132,7 +132,7 @@ void i82801ix_dmi_poll_vc1(void) } timeout = 0x7ffff; - printk(BIOS_DEBUG, "ICH9 waits for port arbitration table update... "); + printk(BIOS_DEBUG, "ICH10 waits for port arbitration table update... "); while ((RCBA32(RCBA_V1STS) & (1 << 0)) && --timeout) {} if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index c40f9b73ea..e2ac852316 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -15,9 +15,9 @@ */ #include -#include "i82801ix.h" +#include "i82801jx.h" -void i82801ix_early_init(void) +void i82801jx_early_init(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index 31b33e92d9..fb6c252d39 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -19,7 +19,7 @@ #include #include #include -#include "i82801ix.h" +#include "i82801jx.h" #include "smbus.h" void enable_smbus(void) @@ -29,11 +29,6 @@ void enable_smbus(void) /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); - /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x2) != 0x2930) { - die("SMBus controller not found!"); - } - /* Set SMBus I/O base. */ pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); diff --git a/src/southbridge/intel/i82801jx/hdaudio.c b/src/southbridge/intel/i82801jx/hdaudio.c index c3602c40b0..c75eee7d3b 100644 --- a/src/southbridge/intel/i82801jx/hdaudio.c +++ b/src/southbridge/intel/i82801jx/hdaudio.c @@ -23,13 +23,13 @@ #include #include #include -#include "i82801ix.h" +#include "i82801jx.h" #define HDA_ICII_REG 0x68 #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1) -typedef struct southbridge_intel_i82801ix_config config_t; +typedef struct southbridge_intel_i82801jx_config config_t; static int set_bits(void *port, u32 mask, u32 val) { @@ -311,9 +311,14 @@ static struct device_operations azalia_ops = { .ops_pci = &azalia_pci_ops, }; -/* ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M */ -static const struct pci_driver i82801ix_azalia __pci_driver = { +static const unsigned short pci_device_ids[] = { + 0x3a3e, + 0x3a6e, + 0 +}; + +static const struct pci_driver i82801jx_azalia __pci_driver = { .ops = &azalia_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x293e, + .devices = pci_device_ids, }; diff --git a/src/southbridge/intel/i82801jx/i82801ix.c b/src/southbridge/intel/i82801jx/i82801ix.c deleted file mode 100644 index 0f3a08c9cf..0000000000 --- a/src/southbridge/intel/i82801jx/i82801ix.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG - * (Written by Nico Huber for secunet) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "i82801ix.h" - -typedef struct southbridge_intel_i82801ix_config config_t; - -static void i82801ix_enable_device(device_t dev) -{ - u32 reg32; - - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); -} - -static void i82801ix_early_settings(const config_t *const info) -{ - /* Program FERR# as processor break event indicator. */ - RCBA32(0x3410) |= (1 << 6); - /* BIOS must program... */ - RCBA32(0x3430) = (RCBA32(0x3430) & ~(0x3 << 0)) | (0x2 << 0); - RCBA32(0x3418) |= (1 << 0); - RCBA32(0x350c) = (RCBA32(0x350c) & ~(0x3 << 26)) | (0x2 << 26); - RCBA32(0x2034) = (RCBA32(0x2034) & ~(0xf << 16)) | (0x5 << 16); - RCBA32(0x0f20) = (RCBA32(0x0f20) & ~(0xf << 16)) | (0x5 << 16); - RCBA32(0x1d40) |= (1 << 0); - RCBA32(0x352c) |= (3 << 16); -} - -static void i82801ix_pcie_init(const config_t *const info) -{ - device_t pciePort[6]; - int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */ - u32 reg32; - - /* PCIe - BIOS must program... */ - for (i = 0; i < 6; ++i) { - pciePort[i] = dev_find_slot(0, PCI_DEVFN(0x1c, i)); - if (!pciePort[i]) { - printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); - die(" is not listed in devicetree.\n"); - } - reg32 = pci_read_config32(pciePort[i], 0x300); - pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); - pci_write_config8(pciePort[i], 0x324, 0x40); - } - - if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) { - for (i = 0; i < 6; ++i) { - if (pciePort[i]->enabled) { - reg32 = pci_read_config32(pciePort[i], 0xe8); - reg32 |= 1; - pci_write_config32(pciePort[i], 0xe8, reg32); - } - } - } - - for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) { - /* Only for the top disabled ports. */ - reg32 = pci_read_config32(pciePort[i], 0x300); - reg32 |= 0x3 << 16; - pci_write_config32(pciePort[i], 0x300, reg32); - } - - /* Set slot implemented, slot number and slot power limits. */ - for (i = 0; i < 6; ++i) { - const device_t dev = pciePort[i]; - u32 xcap = pci_read_config32(dev, D28Fx_XCAP); - if (info->pcie_slot_implemented & (1 << i)) - xcap |= PCI_EXP_FLAGS_SLOT; - else - xcap &= ~PCI_EXP_FLAGS_SLOT; - pci_write_config32(dev, D28Fx_XCAP, xcap); - - if (info->pcie_slot_implemented & (1 << i)) { - u32 slcap = pci_read_config32(dev, D28Fx_SLCAP); - slcap &= ~(0x1fff << 19); - slcap |= (slot_number++ << 19); - slcap &= ~(0x0003 << 16); - slcap |= (info->pcie_power_limits[i].scale << 16); - slcap &= ~(0x00ff << 7); - slcap |= (info->pcie_power_limits[i].value << 7); - pci_write_config32(dev, D28Fx_SLCAP, slcap); - } - } - - /* Lock R/WO ASPM support bits. */ - for (i = 0; i < 6; ++i) { - reg32 = pci_read_config32(pciePort[i], 0x4c); - pci_write_config32(pciePort[i], 0x4c, reg32); - } -} - -static void i82801ix_ehci_init(void) -{ - const device_t pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7)); - if (!pciEHCI1) - die("EHCI controller (00:1d.7) not listed in devicetree.\n"); - const device_t pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7)); - if (!pciEHCI2) - die("EHCI controller (00:1a.7) not listed in devicetree.\n"); - - u32 reg32; - - /* TODO: Maybe we have to save and - restore these settings across S3. */ - reg32 = pci_read_config32(pciEHCI1, 0xfc); - pci_write_config32(pciEHCI1, 0xfc, (reg32 & ~(3 << 2)) | - (1 << 29) | (1 << 17) | (2 << 2)); - reg32 = pci_read_config32(pciEHCI2, 0xfc); - pci_write_config32(pciEHCI2, 0xfc, (reg32 & ~(3 << 2)) | - (1 << 29) | (1 << 17) | (2 << 2)); -} - -static int i82801ix_function_disabled(const unsigned devfn) -{ - const struct device *const dev = dev_find_slot(0, devfn); - if (!dev) { - printk(BIOS_EMERG, - "PCI device 00:%x.%x", - PCI_SLOT(devfn), PCI_FUNC(devfn)); - die(" is not listed in devicetree.\n"); - } - return !dev->enabled; -} - -static void i82801ix_hide_functions(void) -{ - int i; - u32 reg32; - - /* FIXME: This works pretty good if the devicetree is consistent. But - some functions have to be disabled in right order and/or have - other constraints. */ - - if (i82801ix_function_disabled(PCI_DEVFN(0x19, 0))) - RCBA32(RCBA_BUC) |= BUC_LAND; - - reg32 = RCBA32(RCBA_FD); - struct { - int devfn; - u32 mask; - } functions[] = { - { PCI_DEVFN(0x1a, 0), FD_U4D }, /* UHCI #4 */ - { PCI_DEVFN(0x1a, 1), FD_U5D }, /* UHCI #5 */ - { PCI_DEVFN(0x1a, 2), FD_U6D }, /* UHCI #6 */ - { PCI_DEVFN(0x1a, 7), FD_EHCI2D }, /* EHCI #2 */ - { PCI_DEVFN(0x1b, 0), FD_HDAD }, /* HD Audio */ - { PCI_DEVFN(0x1c, 0), FD_PE1D }, /* PCIe #1 */ - { PCI_DEVFN(0x1c, 1), FD_PE2D }, /* PCIe #2 */ - { PCI_DEVFN(0x1c, 2), FD_PE3D }, /* PCIe #3 */ - { PCI_DEVFN(0x1c, 3), FD_PE4D }, /* PCIe #4 */ - { PCI_DEVFN(0x1c, 4), FD_PE5D }, /* PCIe #5 */ - { PCI_DEVFN(0x1c, 5), FD_PE6D }, /* PCIe #6 */ - { PCI_DEVFN(0x1d, 0), FD_U1D }, /* UHCI #1 */ - { PCI_DEVFN(0x1d, 1), FD_U2D }, /* UHCI #2 */ - { PCI_DEVFN(0x1d, 2), FD_U3D }, /* UHCI #3 */ - { PCI_DEVFN(0x1d, 7), FD_EHCI1D }, /* EHCI #1 */ - { PCI_DEVFN(0x1f, 0), FD_LBD }, /* LPC */ - { PCI_DEVFN(0x1f, 2), FD_SAD1 }, /* SATA #1 */ - { PCI_DEVFN(0x1f, 3), FD_SD }, /* SMBus */ - { PCI_DEVFN(0x1f, 5), FD_SAD2 }, /* SATA #2 */ - { PCI_DEVFN(0x1f, 6), FD_TTD }, /* Thermal Throttle */ - }; - for (i = 0; i < ARRAY_SIZE(functions); ++i) { - if (i82801ix_function_disabled(functions[i].devfn)) - reg32 |= functions[i].mask; - } - RCBA32(RCBA_FD) = reg32; - RCBA32(RCBA_FD) |= (1 << 0); /* BIOS must write this... */ - RCBA32(RCBA_FDSW) |= (1 << 7); /* Lock function-disable? */ - - /* Hide PCIe root port PCI functions. RPFN is partially R/WO. */ - reg32 = RCBA32(RCBA_RPFN); - for (i = 0; i < 6; ++i) { - if (i82801ix_function_disabled(PCI_DEVFN(0x1c, i))) - reg32 |= (1 << ((i * 4) + 3)); - } - RCBA32(RCBA_RPFN) = reg32; - - /* Lock R/WO UHCI controller #6 remapping. */ - RCBA32(RCBA_MAP) = RCBA32(RCBA_MAP); -} - -static void i82801ix_init(void *chip_info) -{ - const config_t *const info = (config_t *)chip_info; - - printk(BIOS_DEBUG, "Initializing i82801ix southbridge...\n"); - - i82801ix_early_settings(info); - - /* PCI Express setup. */ - i82801ix_pcie_init(info); - - /* EHCI configuration. */ - i82801ix_ehci_init(); - - /* Now hide internal functions. We can't access them after this. */ - i82801ix_hide_functions(); - - /* Reset watchdog timer. */ -#if !CONFIG_HAVE_SMI_HANDLER - outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ -#endif - outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ -} - -struct chip_operations southbridge_intel_i82801ix_ops = { - CHIP_NAME("Intel ICH9/ICH9-M (82801Ix) Series Southbridge") - .enable_dev = i82801ix_enable_device, - .init = i82801ix_init, -}; diff --git a/src/southbridge/intel/i82801jx/i82801ix.h b/src/southbridge/intel/i82801jx/i82801ix.h deleted file mode 100644 index 6ec6d3f9bd..0000000000 --- a/src/southbridge/intel/i82801jx/i82801ix.h +++ /dev/null @@ -1,232 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * Copyright (C) 2008-2009 coresystems GmbH - * 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H -#define SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H - -#ifndef __ACPI__ -#ifndef __ASSEMBLER__ -#include "chip.h" -#endif -#endif - -#define DEFAULT_TBAR ((u8 *)0xfed1b000) -#ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) -#else -#define DEFAULT_RCBA 0xfed1c000 -#endif - -#define DEFAULT_PMBASE 0x00000500 -#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) -#define DEFAULT_GPIOBASE 0x00000580 - - -#define APM_CNT 0xb2 - -#define PM1_STS 0x00 -#define PWRBTN_STS (1 << 8) -#define RTC_STS (1 << 10) -#define PM1_EN 0x02 -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define PM1_CNT 0x04 -#define SCI_EN (1 << 0) -#define PM_LV2 0x14 -#define PM_LV3 0x15 -#define PM_LV4 0x16 -#define PM_LV5 0x17 -#define PM_LV6 0x18 -#define GPE0_STS 0x20 -#define SMI_EN 0x30 -#define PERIODIC_EN (1 << 14) -#define TCO_EN (1 << 13) -#define APMC_EN (1 << 5) -#define BIOS_EN (1 << 2) -#define EOS (1 << 1) -#define GBL_SMI_EN (1 << 0) -#define SMI_STS 0x34 -#define ALT_GP_SMI_EN 0x38 -#define ALT_GP_SMI_STS 0x3a - - -#define GP_IO_USE_SEL 0x00 -#define GP_IO_SEL 0x04 -#define GP_LVL 0x0c -#define GPO_BLINK 0x18 -#define GPI_INV 0x2c -#define GP_IO_USE_SEL2 0x30 -#define GP_IO_SEL2 0x34 -#define GP_LVL2 0x38 - -#define DEBUG_PERIODIC_SMIS 0 - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 -#define MAINBOARD_POWER_KEEP 2 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - - -/* D31:F0 LPC bridge */ -#define D31F0_PMBASE 0x40 -#define D31F0_ACPI_CNTL 0x44 -#define D31F0_GPIO_BASE 0x48 -#define D31F0_GPIO_CNTL 0x4c -#define D31F0_PIRQA_ROUT 0x60 -#define D31F0_PIRQB_ROUT 0x61 -#define D31F0_PIRQC_ROUT 0x62 -#define D31F0_PIRQD_ROUT 0x63 -#define D31F0_SERIRQ_CNTL 0x64 -#define D31F0_PIRQE_ROUT 0x68 -#define D31F0_PIRQF_ROUT 0x69 -#define D31F0_PIRQG_ROUT 0x6a -#define D31F0_PIRQH_ROUT 0x6b -#define D31F0_LPC_IODEC 0x80 -#define D31F0_LPC_EN 0x82 -#define D31F0_GEN1_DEC 0x84 -#define D31F0_GEN2_DEC 0x88 -#define D31F0_GEN3_DEC 0x8c -#define D31F0_GEN4_DEC 0x90 -#define D31F0_GEN_PMCON_1 0xa0 -#define D31F0_GEN_PMCON_3 0xa4 -#define D31F0_C5_EXIT_TIMING 0xa8 -#define D31F0_CxSTATE_CNF 0xa9 -#define D31F0_C4TIMING_CNT 0xaa -#define D31F0_GPIO_ROUT 0xb8 -#define D31F0_RCBA 0xf0 - -/* GEN_PMCON_3 bits */ -#define RTC_BATTERY_DEAD (1 << 2) -#define RTC_POWER_FAILED (1 << 1) -#define SLEEP_AFTER_POWER_FAIL (1 << 0) - - -/* D31:F2 SATA */ -#define D31F2_IDE_TIM_PRI 0x40 -#define D31F2_IDE_TIM_SEC 0x42 -#define D31F2_SIDX 0xa0 -#define D31F2_SDAT 0xa4 - - -/* D30:F0 PCI-to-PCI bridge */ -#define D30F0_SMLT 0x1b - - -/* D28:F0-5 PCIe root ports */ -#define D28Fx_XCAP 0x42 -#define D28Fx_SLCAP 0x54 - - -#define SMBUS_IO_BASE 0x0400 - -/* PCI Configuration Space (D31:F3): SMBus */ -#define SMB_BASE 0x20 -#define HOSTC 0x40 - -/* HOSTC bits */ -#define I2C_EN (1 << 2) -#define SMB_SMI_EN (1 << 1) -#define HST_EN (1 << 0) - -/* SMBus I/O bits. */ -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -#define SMBUS_TIMEOUT (10 * 1000 * 100) - - -#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) -#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) -#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) - -#define RCBA_V0CTL 0x0014 -#define RCBA_V1CAP 0x001c -#define RCBA_V1CTL 0x0020 -#define RCBA_V1STS 0x0026 -#define RCBA_PAT 0x0030 -#define RCBA_ESD 0x0104 -#define RCBA_ULD 0x0110 -#define RCBA_ULBA 0x0118 -#define RCBA_LCAP 0x01a4 -#define RCBA_LCTL 0x01a8 -#define RCBA_LSTS 0x01aa -#define RCBA_DMIC 0x0234 -#define RCBA_RPFN 0x0238 -#define RCBA_DMC 0x2010 -#define RCBA_HPTC 0x3404 -#define RCBA_BUC 0x3414 -#define RCBA_FD 0x3418 /* Function Disable, see below. */ -#define RCBA_CG 0x341c -#define RCBA_FDSW 0x3420 -#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */ - -#define BUC_LAND (1 << 5) /* LAN */ -#define FD_SAD2 (1 << 25) /* SATA #2 */ -#define FD_TTD (1 << 24) /* Thermal Throttle */ -#define FD_PE6D (1 << 21) /* PCIe root port 6 */ -#define FD_PE5D (1 << 20) /* PCIe root port 5 */ -#define FD_PE4D (1 << 19) /* PCIe root port 4 */ -#define FD_PE3D (1 << 18) /* PCIe root port 3 */ -#define FD_PE2D (1 << 17) /* PCIe root port 2 */ -#define FD_PE1D (1 << 16) /* PCIe root port 1 */ -#define FD_EHCI1D (1 << 15) /* EHCI #1 */ -#define FD_LBD (1 << 14) /* LPC bridge */ -#define FD_EHCI2D (1 << 13) /* EHCI #2 */ -#define FD_U5D (1 << 12) /* UHCI #5 */ -#define FD_U4D (1 << 11) /* UHCI #4 */ -#define FD_U3D (1 << 10) /* UHCI #3 */ -#define FD_U2D (1 << 9) /* UHCI #2 */ -#define FD_U1D (1 << 8) /* UHCI #1 */ -#define FD_U6D (1 << 7) /* UHCI #6 */ -#define FD_HDAD (1 << 4) /* HD audio */ -#define FD_SD (1 << 3) /* SMBus */ -#define FD_SAD1 (1 << 2) /* SATA #1 */ - - -#ifndef __ACPI__ -#ifndef __ASSEMBLER__ - -static inline int lpc_is_mobile(const u16 devid) -{ - return (devid == 0x2917) || (devid == 0x2919); -} -#define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) - -#if defined(__PRE_RAM__) -void enable_smbus(void); -int smbus_read_byte(unsigned device, unsigned address); -void i82801ix_early_init(void); -void i82801ix_dmi_setup(void); -void i82801ix_dmi_poll_vc1(void); -#endif - -#endif -#endif - -#endif diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c new file mode 100644 index 0000000000..dca3a4142e --- /dev/null +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * (Written by Nico Huber for secunet) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "i82801jx.h" + +typedef struct southbridge_intel_i82801jx_config config_t; + +static void i82801jx_enable_device(device_t dev) +{ + u32 reg32; + + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); +} + +static void i82801jx_early_settings(const config_t *const info) +{ + /* Program FERR# as processor break event indicator. */ + RCBA32(0x3410) |= (1 << 6); + /* BIOS must program... */ + RCBA32(0x3430) = (RCBA32(0x3430) & ~(0x3 << 0)) | (0x2 << 0); + RCBA32(0x3418) |= (1 << 0); + RCBA32(0x350c) = (RCBA32(0x350c) & ~(0x3 << 26)) | (0x2 << 26); + RCBA32(0x2034) = (RCBA32(0x2034) & ~(0xf << 16)) | (0x5 << 16); + RCBA32(0x0f20) = (RCBA32(0x0f20) & ~(0xf << 16)) | (0x5 << 16); + RCBA32(0x1d40) |= (1 << 0); + RCBA32(0x352c) |= (3 << 16); +} + +static void i82801jx_pcie_init(const config_t *const info) +{ + device_t pciePort[6]; + int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */ + u32 reg32; + + /* PCIe - BIOS must program... */ + for (i = 0; i < 6; ++i) { + pciePort[i] = dev_find_slot(0, PCI_DEVFN(0x1c, i)); + if (!pciePort[i]) { + printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); + die(" is not listed in devicetree.\n"); + } + reg32 = pci_read_config32(pciePort[i], 0x300); + pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); + pci_write_config8(pciePort[i], 0x324, 0x40); + } + + if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) { + for (i = 0; i < 6; ++i) { + if (pciePort[i]->enabled) { + reg32 = pci_read_config32(pciePort[i], 0xe8); + reg32 |= 1; + pci_write_config32(pciePort[i], 0xe8, reg32); + } + } + } + + for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) { + /* Only for the top disabled ports. */ + reg32 = pci_read_config32(pciePort[i], 0x300); + reg32 |= 0x3 << 16; + pci_write_config32(pciePort[i], 0x300, reg32); + } + + /* Set slot implemented, slot number and slot power limits. */ + for (i = 0; i < 6; ++i) { + const device_t dev = pciePort[i]; + u32 xcap = pci_read_config32(dev, D28Fx_XCAP); + if (info->pcie_slot_implemented & (1 << i)) + xcap |= PCI_EXP_FLAGS_SLOT; + else + xcap &= ~PCI_EXP_FLAGS_SLOT; + pci_write_config32(dev, D28Fx_XCAP, xcap); + + if (info->pcie_slot_implemented & (1 << i)) { + u32 slcap = pci_read_config32(dev, D28Fx_SLCAP); + slcap &= ~(0x1fff << 19); + slcap |= (slot_number++ << 19); + slcap &= ~(0x0003 << 16); + slcap |= (info->pcie_power_limits[i].scale << 16); + slcap &= ~(0x00ff << 7); + slcap |= (info->pcie_power_limits[i].value << 7); + pci_write_config32(dev, D28Fx_SLCAP, slcap); + } + } + + /* Lock R/WO ASPM support bits. */ + for (i = 0; i < 6; ++i) { + reg32 = pci_read_config32(pciePort[i], 0x4c); + pci_write_config32(pciePort[i], 0x4c, reg32); + } +} + +static void i82801jx_ehci_init(void) +{ + const device_t pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7)); + if (!pciEHCI1) + die("EHCI controller (00:1d.7) not listed in devicetree.\n"); + const device_t pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7)); + if (!pciEHCI2) + die("EHCI controller (00:1a.7) not listed in devicetree.\n"); + + u32 reg32; + + /* TODO: Maybe we have to save and + restore these settings across S3. */ + reg32 = pci_read_config32(pciEHCI1, 0xfc); + pci_write_config32(pciEHCI1, 0xfc, (reg32 & ~(3 << 2)) | + (1 << 29) | (1 << 17) | (2 << 2)); + reg32 = pci_read_config32(pciEHCI2, 0xfc); + pci_write_config32(pciEHCI2, 0xfc, (reg32 & ~(3 << 2)) | + (1 << 29) | (1 << 17) | (2 << 2)); +} + +static int i82801jx_function_disabled(const unsigned int devfn) +{ + const struct device *const dev = dev_find_slot(0, devfn); + if (!dev) { + printk(BIOS_EMERG, + "PCI device 00:%x.%x", + PCI_SLOT(devfn), PCI_FUNC(devfn)); + die(" is not listed in devicetree.\n"); + } + return !dev->enabled; +} + +static void i82801jx_hide_functions(void) +{ + int i; + u32 reg32; + + /* FIXME: This works pretty good if the devicetree is consistent. But + some functions have to be disabled in right order and/or have + other constraints. */ + + if (i82801jx_function_disabled(PCI_DEVFN(0x19, 0))) + RCBA32(RCBA_BUC) |= BUC_LAND; + + reg32 = RCBA32(RCBA_FD); + struct { + int devfn; + u32 mask; + } functions[] = { + { PCI_DEVFN(0x1a, 0), FD_U4D }, /* UHCI #4 */ + { PCI_DEVFN(0x1a, 1), FD_U5D }, /* UHCI #5 */ + { PCI_DEVFN(0x1a, 2), FD_U6D }, /* UHCI #6 */ + { PCI_DEVFN(0x1a, 7), FD_EHCI2D }, /* EHCI #2 */ + { PCI_DEVFN(0x1b, 0), FD_HDAD }, /* HD Audio */ + { PCI_DEVFN(0x1c, 0), FD_PE1D }, /* PCIe #1 */ + { PCI_DEVFN(0x1c, 1), FD_PE2D }, /* PCIe #2 */ + { PCI_DEVFN(0x1c, 2), FD_PE3D }, /* PCIe #3 */ + { PCI_DEVFN(0x1c, 3), FD_PE4D }, /* PCIe #4 */ + { PCI_DEVFN(0x1c, 4), FD_PE5D }, /* PCIe #5 */ + { PCI_DEVFN(0x1c, 5), FD_PE6D }, /* PCIe #6 */ + { PCI_DEVFN(0x1d, 0), FD_U1D }, /* UHCI #1 */ + { PCI_DEVFN(0x1d, 1), FD_U2D }, /* UHCI #2 */ + { PCI_DEVFN(0x1d, 2), FD_U3D }, /* UHCI #3 */ + { PCI_DEVFN(0x1d, 7), FD_EHCI1D }, /* EHCI #1 */ + { PCI_DEVFN(0x1f, 0), FD_LBD }, /* LPC */ + { PCI_DEVFN(0x1f, 2), FD_SAD1 }, /* SATA #1 */ + { PCI_DEVFN(0x1f, 3), FD_SD }, /* SMBus */ + { PCI_DEVFN(0x1f, 5), FD_SAD2 }, /* SATA #2 */ + { PCI_DEVFN(0x1f, 6), FD_TTD }, /* Thermal Throttle */ + }; + for (i = 0; i < ARRAY_SIZE(functions); ++i) { + if (i82801jx_function_disabled(functions[i].devfn)) + reg32 |= functions[i].mask; + } + RCBA32(RCBA_FD) = reg32; + RCBA32(RCBA_FD) |= (1 << 0); /* BIOS must write this... */ + RCBA32(RCBA_FDSW) |= (1 << 7); /* Lock function-disable? */ + + /* Hide PCIe root port PCI functions. RPFN is partially R/WO. */ + reg32 = RCBA32(RCBA_RPFN); + for (i = 0; i < 6; ++i) { + if (i82801jx_function_disabled(PCI_DEVFN(0x1c, i))) + reg32 |= (1 << ((i * 4) + 3)); + } + RCBA32(RCBA_RPFN) = reg32; + + /* Lock R/WO UHCI controller #6 remapping. */ + RCBA32(RCBA_MAP) = RCBA32(RCBA_MAP); +} + +static void i82801jx_init(void *chip_info) +{ + const config_t *const info = (config_t *)chip_info; + + printk(BIOS_DEBUG, "Initializing i82801jx southbridge...\n"); + + i82801jx_early_settings(info); + + /* PCI Express setup. */ + i82801jx_pcie_init(info); + + /* EHCI configuration. */ + i82801jx_ehci_init(); + + /* Now hide internal functions. We can't access them after this. */ + i82801jx_hide_functions(); + + /* Reset watchdog timer. */ +#if !CONFIG_HAVE_SMI_HANDLER + outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ +#endif + outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ +} + +struct chip_operations southbridge_intel_i82801jx_ops = { + CHIP_NAME("Intel ICH10 (82801Jx) Series Southbridge") + .enable_dev = i82801jx_enable_device, + .init = i82801jx_init, +}; diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h new file mode 100644 index 0000000000..1c765a3d9c --- /dev/null +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -0,0 +1,234 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson , Raptor Engineering + * Copyright (C) 2008-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H +#define SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H + +#ifndef __ACPI__ +#ifndef __ASSEMBLER__ +#include "chip.h" +#endif +#endif + +#define DEFAULT_TBAR ((u8 *)0xfed1b000) +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else +#define DEFAULT_RCBA 0xfed1c000 +#endif + +#define DEFAULT_PMBASE 0x00000500 +#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) +#define DEFAULT_GPIOBASE 0x00000580 + + +#define APM_CNT 0xb2 + +#define PM1_STS 0x00 +#define PWRBTN_STS (1 << 8) +#define RTC_STS (1 << 10) +#define PM1_EN 0x02 +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define PM1_CNT 0x04 +#define SCI_EN (1 << 0) +#define PM_LV2 0x14 +#define PM_LV3 0x15 +#define PM_LV4 0x16 +#define PM_LV5 0x17 +#define PM_LV6 0x18 +#define GPE0_STS 0x20 +#define SMI_EN 0x30 +#define PERIODIC_EN (1 << 14) +#define TCO_EN (1 << 13) +#define APMC_EN (1 << 5) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define ALT_GP_SMI_EN 0x38 +#define ALT_GP_SMI_STS 0x3a + + +#define GP_IO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GP_IO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 + +#define DEBUG_PERIODIC_SMIS 0 + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + + +/* D31:F0 LPC bridge */ +#define D31F0_PMBASE 0x40 +#define PMBASE D31F0_PMBASE +#define D31F0_ACPI_CNTL 0x44 +#define ACPI_CNTL D31F0_ACPI_CNTL +#define D31F0_GPIO_BASE 0x48 +#define D31F0_GPIO_CNTL 0x4c +#define D31F0_PIRQA_ROUT 0x60 +#define D31F0_PIRQB_ROUT 0x61 +#define D31F0_PIRQC_ROUT 0x62 +#define D31F0_PIRQD_ROUT 0x63 +#define D31F0_SERIRQ_CNTL 0x64 +#define D31F0_PIRQE_ROUT 0x68 +#define D31F0_PIRQF_ROUT 0x69 +#define D31F0_PIRQG_ROUT 0x6a +#define D31F0_PIRQH_ROUT 0x6b +#define D31F0_LPC_IODEC 0x80 +#define D31F0_LPC_EN 0x82 +#define D31F0_GEN1_DEC 0x84 +#define D31F0_GEN2_DEC 0x88 +#define D31F0_GEN3_DEC 0x8c +#define D31F0_GEN4_DEC 0x90 +#define D31F0_GEN_PMCON_1 0xa0 +#define D31F0_GEN_PMCON_3 0xa4 +#define D31F0_C5_EXIT_TIMING 0xa8 +#define D31F0_CxSTATE_CNF 0xa9 +#define D31F0_C4TIMING_CNT 0xaa +#define D31F0_GPIO_ROUT 0xb8 +#define D31F0_RCBA 0xf0 + +/* GEN_PMCON_3 bits */ +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + + +/* D31:F2 SATA */ +#define D31F2_IDE_TIM_PRI 0x40 +#define D31F2_IDE_TIM_SEC 0x42 +#define D31F2_SIDX 0xa0 +#define D31F2_SDAT 0xa4 + + +/* D30:F0 PCI-to-PCI bridge */ +#define D30F0_SMLT 0x1b + + +/* D28:F0-5 PCIe root ports */ +#define D28Fx_XCAP 0x42 +#define D28Fx_SLCAP 0x54 + + +#define SMBUS_IO_BASE 0x0400 + +/* PCI Configuration Space (D31:F3): SMBus */ +#define SMB_BASE 0x20 +#define HOSTC 0x40 + +/* HOSTC bits */ +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +/* SMBus I/O bits. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +#define SMBUS_TIMEOUT (10 * 1000 * 100) + + +#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) +#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) +#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) + +#define RCBA_V0CTL 0x0014 +#define RCBA_V1CAP 0x001c +#define RCBA_V1CTL 0x0020 +#define RCBA_V1STS 0x0026 +#define RCBA_PAT 0x0030 +#define RCBA_ESD 0x0104 +#define RCBA_ULD 0x0110 +#define RCBA_ULBA 0x0118 +#define RCBA_LCAP 0x01a4 +#define RCBA_LCTL 0x01a8 +#define RCBA_LSTS 0x01aa +#define RCBA_DMIC 0x0234 +#define RCBA_RPFN 0x0238 +#define RCBA_DMC 0x2010 +#define RCBA_HPTC 0x3404 +#define RCBA_BUC 0x3414 +#define RCBA_FD 0x3418 /* Function Disable, see below. */ +#define RCBA_CG 0x341c +#define RCBA_FDSW 0x3420 +#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */ + +#define BUC_LAND (1 << 5) /* LAN */ +#define FD_SAD2 (1 << 25) /* SATA #2 */ +#define FD_TTD (1 << 24) /* Thermal Throttle */ +#define FD_PE6D (1 << 21) /* PCIe root port 6 */ +#define FD_PE5D (1 << 20) /* PCIe root port 5 */ +#define FD_PE4D (1 << 19) /* PCIe root port 4 */ +#define FD_PE3D (1 << 18) /* PCIe root port 3 */ +#define FD_PE2D (1 << 17) /* PCIe root port 2 */ +#define FD_PE1D (1 << 16) /* PCIe root port 1 */ +#define FD_EHCI1D (1 << 15) /* EHCI #1 */ +#define FD_LBD (1 << 14) /* LPC bridge */ +#define FD_EHCI2D (1 << 13) /* EHCI #2 */ +#define FD_U5D (1 << 12) /* UHCI #5 */ +#define FD_U4D (1 << 11) /* UHCI #4 */ +#define FD_U3D (1 << 10) /* UHCI #3 */ +#define FD_U2D (1 << 9) /* UHCI #2 */ +#define FD_U1D (1 << 8) /* UHCI #1 */ +#define FD_U6D (1 << 7) /* UHCI #6 */ +#define FD_HDAD (1 << 4) /* HD audio */ +#define FD_SD (1 << 3) /* SMBus */ +#define FD_SAD1 (1 << 2) /* SATA #1 */ + + +#ifndef __ACPI__ +#ifndef __ASSEMBLER__ + +static inline int lpc_is_mobile(const u16 devid) +{ + return (devid == 0x2917) || (devid == 0x2919); +} +#define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) + +#if defined(__PRE_RAM__) +void enable_smbus(void); +int smbus_read_byte(unsigned device, unsigned address); +void i82801jx_early_init(void); +void i82801jx_dmi_setup(void); +void i82801jx_dmi_poll_vc1(void); +#endif + +#endif +#endif + +#endif diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 8212b0a092..5d3b6b5d65 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -30,7 +30,7 @@ #include #include #include -#include "i82801ix.h" +#include "i82801jx.h" #include "nvs.h" #include #include @@ -40,9 +40,9 @@ #define ENABLE_ACPI_MODE_IN_COREBOOT 0 #define TEST_SMM_FLASH_LOCKDOWN 0 -typedef struct southbridge_intel_i82801ix_config config_t; +typedef struct southbridge_intel_i82801jx_config config_t; -static void i82801ix_enable_apic(struct device *dev) +static void i82801jx_enable_apic(struct device *dev) { u32 reg32; volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); @@ -62,7 +62,7 @@ static void i82801ix_enable_apic(struct device *dev) setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */ } -static void i82801ix_enable_serial_irqs(struct device *dev) +static void i82801jx_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, D31F0_SERIRQ_CNTL, @@ -90,7 +90,7 @@ static void i82801ix_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void i82801ix_pirq_init(device_t dev) +static void i82801jx_pirq_init(device_t dev) { device_t irq_dev; /* Get the chip configuration */ @@ -132,7 +132,7 @@ static void i82801ix_pirq_init(device_t dev) } } -static void i82801ix_gpi_routing(device_t dev) +static void i82801jx_gpi_routing(device_t dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -161,7 +161,7 @@ static void i82801ix_gpi_routing(device_t dev) pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); } -static void i82801ix_power_options(device_t dev) +static void i82801jx_power_options(device_t dev) { u8 reg8; u16 reg16, pmbase; @@ -245,7 +245,7 @@ static void i82801ix_power_options(device_t dev) // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only #if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using + /* Set DEBUG_PERIODIC_SMIS in i82801jx.h to debug using * periodic SMIs. */ reg16 |= (3 << 0); // Periodic SMI every 8s @@ -268,7 +268,7 @@ static void i82801ix_power_options(device_t dev) } // Set the board's GPI routing. - i82801ix_gpi_routing(dev); + i82801jx_gpi_routing(dev); pmbase = pci_read_config16(dev, 0x40) & 0xfffe; @@ -293,7 +293,7 @@ static void i82801ix_power_options(device_t dev) outl(reg32, pmbase + 0x10); } -static void i82801ix_configure_cstates(device_t dev) +static void i82801jx_configure_cstates(device_t dev) { u8 reg8; @@ -311,7 +311,7 @@ static void i82801ix_configure_cstates(device_t dev) /* We could enable slow-C4 exit here, if someone needs it? */ } -static void i82801ix_rtc_init(struct device *dev) +static void i82801jx_rtc_init(struct device *dev) { u8 reg8; int rtc_failed; @@ -370,7 +370,7 @@ static void enable_clock_gating(void) } #if CONFIG_HAVE_SMI_HANDLER -static void i82801ix_lock_smm(struct device *dev) +static void i82801jx_lock_smm(struct device *dev) { #if TEST_SMM_FLASH_LOCKDOWN u8 reg8; @@ -426,28 +426,28 @@ static void i82801ix_lock_smm(struct device *dev) static void lpc_init(struct device *dev) { - printk(BIOS_DEBUG, "i82801ix: lpc_init\n"); + printk(BIOS_DEBUG, "i82801jx: lpc_init\n"); /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); /* IO APIC initialization. */ - i82801ix_enable_apic(dev); + i82801jx_enable_apic(dev); - i82801ix_enable_serial_irqs(dev); + i82801jx_enable_serial_irqs(dev); /* Setup the PIRQ. */ - i82801ix_pirq_init(dev); + i82801jx_pirq_init(dev); /* Setup power options. */ - i82801ix_power_options(dev); + i82801jx_power_options(dev); /* Configure Cx state registers */ if (LPC_IS_MOBILE(dev)) - i82801ix_configure_cstates(dev); + i82801jx_configure_cstates(dev); /* Initialize the real time clock. */ - i82801ix_rtc_init(dev); + i82801jx_rtc_init(dev); /* Initialize ISA DMA. */ isa_dma_init(); @@ -465,11 +465,11 @@ static void lpc_init(struct device *dev) i8259_configure_irq_trigger(9, 1); #if CONFIG_HAVE_SMI_HANDLER - i82801ix_lock_smm(dev); + i82801jx_lock_smm(dev); #endif } -static void i82801ix_lpc_read_resources(device_t dev) +static void i82801jx_lpc_read_resources(device_t dev) { /* * I/O Resources @@ -571,7 +571,7 @@ static struct pci_operations pci_ops = { }; static struct device_operations device_ops = { - .read_resources = i82801ix_lpc_read_resources, + .read_resources = i82801jx_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, @@ -583,16 +583,16 @@ static struct device_operations device_ops = { }; static const unsigned short pci_device_ids[] = { - 0x2912, /* ICH9DH */ - 0x2914, /* ICH9DO */ - 0x2916, /* ICH9R */ - 0x2918, /* ICH9 */ - 0x2917, /* ICH9M-E */ - 0x2919, /* ICH9M */ + 0x3a10, /* ICH10R Eng. Sample */ + 0x3a14, /* ICH10DO */ + 0x3a16, /* ICH10R */ + 0x3a18, /* ICH10 */ + 0x3a1a, /* ICH10D */ + 0x3a1e, /* ICH10 Eng. Sample */ 0 }; -static const struct pci_driver ich9_lpc __pci_driver = { +static const struct pci_driver ich10_lpc __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, diff --git a/src/southbridge/intel/i82801jx/pci.c b/src/southbridge/intel/i82801jx/pci.c index 5da2e49940..2262c91465 100644 --- a/src/southbridge/intel/i82801jx/pci.c +++ b/src/southbridge/intel/i82801jx/pci.c @@ -17,7 +17,7 @@ #include #include #include -#include "i82801ix.h" +#include "i82801jx.h" static void pci_init(struct device *dev) { @@ -70,12 +70,11 @@ static struct device_operations device_ops = { }; static const unsigned short pci_device_ids[] = { - 0x244e, /* Desktop */ - 0x2448, /* Mobile */ + 0x244e, 0 }; -static const struct pci_driver ich9_pci __pci_driver = { +static const struct pci_driver ich10_pci __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index 502e765773..01f65dee5d 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -27,9 +27,9 @@ static void pci_init(struct device *dev) { u16 reg16; u32 reg32; - struct southbridge_intel_i82801ix_config *config = dev->chip_info; + struct southbridge_intel_i82801jx_config *config = dev->chip_info; - printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n"); + printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n"); /* Enable Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); @@ -108,7 +108,7 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void pch_pciexp_scan_bridge(device_t dev) { - struct southbridge_intel_i82801ix_config *config = dev->chip_info; + struct southbridge_intel_i82801jx_config *config = dev->chip_info; /* Normal PCIe Scan */ pciexp_scan_bridge(dev); @@ -131,17 +131,25 @@ static struct device_operations device_ops = { .ops_pci = &pci_ops, }; -/* 82801Ix (ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M) */ +/* 82801lJx, ICH10 */ static const unsigned short pci_device_ids[] = { - 0x2940, /* Port 1 */ - 0x2942, /* Port 2 */ - 0x2944, /* Port 3 */ - 0x2946, /* Port 4 */ - 0x2948, /* Port 5 */ - 0x294a, /* Port 6 */ + 0x3a40, /* Port 1 */ + 0x3a42, /* Port 2 */ + 0x3a44, /* Port 3 */ + 0x3a46, /* Port 4 */ + 0x3a48, /* Port 5 */ + 0x3a4a, /* Port 6 */ + + 0x3a70, /* Port 1 */ + 0x3a72, /* Port 2 */ + 0x3a74, /* Port 3 */ + 0x3a76, /* Port 4 */ + 0x3a78, /* Port 5 */ + 0x3a7a, /* Port 6 */ 0 }; -static const struct pci_driver ich9_pcie __pci_driver = { + +static const struct pci_driver ich10_pcie __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 8bfc476e8c..9fe1f9ec15 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -20,10 +20,10 @@ #include #include #include -#include "i82801ix.h" +#include "i82801jx.h" #include -typedef struct southbridge_intel_i82801ix_config config_t; +typedef struct southbridge_intel_i82801jx_config config_t; static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, const int is_mobile) @@ -148,10 +148,10 @@ static void sata_init(struct device *const dev) const int is_mobile = (devid == 0x2928) || (devid == 0x2929); u8 sata_mode; - printk(BIOS_DEBUG, "i82801ix_sata: initializing...\n"); + printk(BIOS_DEBUG, "i82801jx_sata: initializing...\n"); if (config == NULL) { - printk(BIOS_ERR, "i82801ix_sata: error: " + printk(BIOS_ERR, "i82801jx_sata: error: " "device not in devicetree.cb!\n"); return; } @@ -277,8 +277,14 @@ static struct device_operations sata_ops = { }; static const unsigned short pci_device_ids[] = { - 0x2920, 0x2921, 0x2922, 0x2923, - 0x2928, 0x2929, + 0x3a00, + 0x3a02, + 0x3a05, + 0x3a06, + 0x3a20, + 0x3a22, + 0x3a25, + 0x3a26, 0, }; diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c index 211372237f..00894cf82a 100644 --- a/src/southbridge/intel/i82801jx/smbus.c +++ b/src/southbridge/intel/i82801jx/smbus.c @@ -103,7 +103,12 @@ static struct device_operations smbus_ops = { .ops_pci = &smbus_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x2930, 0 }; +static const unsigned short pci_device_ids[] = +{ + 0x3a30, + 0x3a60, + 0 +}; static const struct pci_driver pch_smbus __pci_driver = { .ops = &smbus_ops, diff --git a/src/southbridge/intel/i82801jx/smbus.h b/src/southbridge/intel/i82801jx/smbus.h index bcc758700d..61402f77b2 100644 --- a/src/southbridge/intel/i82801jx/smbus.h +++ b/src/southbridge/intel/i82801jx/smbus.h @@ -15,7 +15,7 @@ */ #include -#include "i82801ix.h" +#include "i82801jx.h" static void smbus_delay(void) { diff --git a/src/southbridge/intel/i82801jx/smi.c b/src/southbridge/intel/i82801jx/smi.c index a6c28cbbc2..06fa5856c6 100644 --- a/src/southbridge/intel/i82801jx/smi.c +++ b/src/southbridge/intel/i82801jx/smi.c @@ -25,7 +25,7 @@ #include #include #include -#include "i82801ix.h" +#include "i82801jx.h" /* I945/GM45 */ #define SMRAM 0x9d @@ -276,7 +276,7 @@ static void smm_relocate(void) smi_en |= TCO_EN; smi_en |= APMC_EN; #if DEBUG_PERIODIC_SMIS - /* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using + /* Set DEBUG_PERIODIC_SMIS in i82801jx.h to debug using * periodic SMIs. */ smi_en |= PERIODIC_EN; diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c index 7ad00ed5ba..35e79c6064 100644 --- a/src/southbridge/intel/i82801jx/smihandler.c +++ b/src/southbridge/intel/i82801jx/smihandler.c @@ -22,7 +22,7 @@ #include #include #include -#include "i82801ix.h" +#include "i82801jx.h" #include "nvs.h" diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index 12cf89891f..a5d5bed309 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -20,7 +20,7 @@ #include #include -#include "i82801ix.h" +#include "i82801jx.h" static void thermal_init(struct device *dev) { @@ -74,8 +74,14 @@ static struct device_operations device_ops = { .ops_pci = &thermal_pci_ops, }; -static const struct pci_driver ich9_thermal __pci_driver = { +static const unsigned short pci_device_ids[] = { + 0x3a32, + 0x3a62, + 0 +}; + +static const struct pci_driver ich10_thermal __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x2932, + .devices = pci_device_ids, }; diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c index 7719f16c1d..d5a0d97734 100644 --- a/src/southbridge/intel/i82801jx/usb_ehci.c +++ b/src/southbridge/intel/i82801jx/usb_ehci.c @@ -18,7 +18,7 @@ #include #include #include -#include "i82801ix.h" +#include "i82801jx.h" #include static void usb_ehci_init(struct device *dev) @@ -55,8 +55,10 @@ static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned devic } static const unsigned short pci_device_ids[] = { - 0x293a, - 0x293c, + 0x3a3a, + 0x3a6a, + 0x3a3c, + 0x3a6c, 0 }; -- cgit v1.2.1