diff options
Diffstat (limited to 'libc/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c')
| -rw-r--r-- | libc/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/libc/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c b/libc/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c index 7c02c6898..aed6fa60e 100644 --- a/libc/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c +++ b/libc/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c @@ -24,14 +24,26 @@ extern int __cache_line_size; weak_extern (__cache_line_size) -/* Scan the Aux Vector for the "Data Cache Block Size" entry. If found - verify that the static extern __cache_line_size is defined by checking - for not NULL. If it is defined then assign the cache block size - value to __cache_line_size. */ +/* Scan the Aux Vector for the "Data Cache Block Size" entry. If + found verify that the static extern __cache_line_size is defined by + checking for not NULL. If it is defined then assign the cache + block size value to __cache_line_size. This is used by memset to + optimize setting to zero. We have to detect 8xx processors, which + have buggy dcbz implementations that cannot report page faults + correctly. That requires reading SPR, which is a privileged + operation. Fortunately 2.2.18 and later emulates PowerPC mfspr + reads from the PVR register. */ #define DL_PLATFORM_AUXV \ case AT_DCACHEBSIZE: \ { \ int *cls = & __cache_line_size; \ + if (__LINUX_KERNEL_VERSION >= 0x020218) \ + { \ + unsigned pvr = 0; \ + asm ("mfspr %0, 287" : "=r" (pvr)); \ + if ((pvr & 0xffff0000) == 0x00500000) \ + cls = NULL; \ + } \ if (cls != NULL) \ *cls = av->a_un.a_val; \ } \ |