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| author | Wilson Snyder <wsnyder@wsnyder.org> | 2019-07-06 13:33:59 -0400 |
|---|---|---|
| committer | Wilson Snyder <wsnyder@wsnyder.org> | 2019-07-06 13:33:59 -0400 |
| commit | 99a7a188ec052ffcae06ffe49ffe29ccbc2c50ee (patch) | |
| tree | 7f520dda8909560dc28215ca801e22364dc67b0a /lisp/emacs-lisp/lisp-mode.el | |
| parent | 3a00a56f4281d7f38c917abfac84349349ad42dd (diff) | |
| download | emacs-99a7a188ec052ffcae06ffe49ffe29ccbc2c50ee.tar.gz | |
Fix indentation of default clocking definitions.
* verilog-mode.el (verilog-default-clocking-re): Fix indentation of default
clocking definitions, Verilog-Mode bug1457. Reported by Paul Donahue.
Diffstat (limited to 'lisp/emacs-lisp/lisp-mode.el')
0 files changed, 0 insertions, 0 deletions