summaryrefslogtreecommitdiff
path: root/erts
diff options
context:
space:
mode:
authorJohn Högberg <john@erlang.org>2023-04-17 10:41:34 +0200
committerJohn Högberg <john@erlang.org>2023-04-17 10:41:34 +0200
commit976d2c401ac74d948e1547c0c5e06e1116a90101 (patch)
treef9ce807d28a8fd85fdb15827ebac6417b7d7b1aa /erts
parent5675c7dd3dc1727332596c67215109f7b217ecfa (diff)
parent249d283ab7eda6e5b17c27ef8f7a4d0d2c70a3af (diff)
downloaderlang-976d2c401ac74d948e1547c0c5e06e1116a90101.tar.gz
Merge branch 'maint'
* maint: Update configure scripts erts: Fix ic/dc config tests and usage
Diffstat (limited to 'erts')
-rwxr-xr-xerts/configure28
-rw-r--r--erts/configure.ac21
-rw-r--r--erts/emulator/beam/jit/beam_jit_main.cpp6
3 files changed, 47 insertions, 8 deletions
diff --git a/erts/configure b/erts/configure
index 2c76bc1587..64db499912 100755
--- a/erts/configure
+++ b/erts/configure
@@ -14193,7 +14193,7 @@ int
main (void)
{
- __asm__ __volatile__("isb sy" : : : "memory");
+ __asm__ __volatile__("isb sy\n" : : : "memory");
;
return 0;
@@ -14227,7 +14227,7 @@ int
main (void)
{
- char data[512]; __asm__ __volatile__("dc cvau, %0" : "r" (data) : : "memory");
+ char data[512]; __asm__ __volatile__("dc cvau, %0\n" :: "r" (data) : "memory");
;
return 0;
@@ -14261,7 +14261,7 @@ int
main (void)
{
- char data[512]; __asm__ __volatile__("ic ivau, %0" : "r" (data) : : "memory");
+ char data[512]; __asm__ __volatile__("ic ivau, %0\n" :: "r" (data) : "memory");
;
return 0;
@@ -24539,7 +24539,27 @@ then :
JIT_ARCH=x86
;;
arm64)
- JIT_ARCH=arm
+ case "$OPSYS" in
+ win32|darwin)
+ # These platforms have dedicated system calls for clearing
+ # instruction cache, and don't require us to manually issue
+ # instruction barriers on all threads.
+ JIT_ARCH=arm
+ ;;
+ *)
+ # We need to use `DC CVAU`, `IC IVAU`, and `ISB SY` to clear
+ # instruction cache. These have already been tested as part of
+ # ETHR_CHK_GCC_ATOMIC_OPS([]).
+
+ if test "$ethr_arm_isb_sy_instr_val$ethr_arm_dc_cvau_instr_val$ethr_arm_ic_ivau_instr_val" = "111"; then
+ JIT_ARCH=arm
+ else
+ enable_jit=no
+ { printf "%s\n" "$as_me:${as_lineno-$LINENO}: WARNING: JIT disabled due to lack of cache-clearing instructions" >&5
+printf "%s\n" "$as_me: WARNING: JIT disabled due to lack of cache-clearing instructions" >&2;}
+ fi
+ ;;
+ esac
;;
*)
if test ${enable_jit} = yes; then
diff --git a/erts/configure.ac b/erts/configure.ac
index b0ffc684b3..d614637830 100644
--- a/erts/configure.ac
+++ b/erts/configure.ac
@@ -2855,7 +2855,26 @@ AS_IF([test ${enable_jit} != no],
JIT_ARCH=x86
;;
arm64)
- JIT_ARCH=arm
+ case "$OPSYS" in
+ win32|darwin)
+ # These platforms have dedicated system calls for clearing
+ # instruction cache, and don't require us to manually issue
+ # instruction barriers on all threads.
+ JIT_ARCH=arm
+ ;;
+ *)
+ # We need to use `DC CVAU`, `IC IVAU`, and `ISB SY` to clear
+ # instruction cache. These have already been tested as part of
+ # ETHR_CHK_GCC_ATOMIC_OPS([]).
+
+ if test "$ethr_arm_isb_sy_instr_val$ethr_arm_dc_cvau_instr_val$ethr_arm_ic_ivau_instr_val" = "111"; then
+ JIT_ARCH=arm
+ else
+ enable_jit=no
+ AC_MSG_WARN([JIT disabled due to lack of cache-clearing instructions])
+ fi
+ ;;
+ esac
;;
*)
if test ${enable_jit} = yes; then
diff --git a/erts/emulator/beam/jit/beam_jit_main.cpp b/erts/emulator/beam/jit/beam_jit_main.cpp
index 7cd8dbf2aa..0cd732039f 100644
--- a/erts/emulator/beam/jit/beam_jit_main.cpp
+++ b/erts/emulator/beam/jit/beam_jit_main.cpp
@@ -421,9 +421,9 @@ extern "C"
/* Issues full memory/instruction barriers on all threads for us. */
sys_icache_invalidate((char *)address, size);
#elif defined(__aarch64__) && defined(__GNUC__) && \
- defined(ETHR_HAVE_GCC_ASM_ARM_IC_IVAU_INSTRUCTION) && \
- defined(ETHR_HAVE_GCC_ASM_ARM_DC_CVAU_INSTRUCTION) && \
- defined(ERTS_THR_INSTRUCTION_BARRIER)
+ defined(ERTS_THR_INSTRUCTION_BARRIER) && \
+ ETHR_HAVE_GCC_ASM_ARM_IC_IVAU_INSTRUCTION && \
+ ETHR_HAVE_GCC_ASM_ARM_DC_CVAU_INSTRUCTION
/* Note that we do not issue any barriers here, whether instruction or
* memory. This is on purpose as we must issue those on all schedulers
* and not just the calling thread, and the chances of us forgetting to