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* flashrom 0.9.1-rc1 tagflashrom-0.9.1-rc1hailfinger2009-08-180-0/+0
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/tags/flashrom-0.9.1-rc1@687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix compilation on Nexenta which is Ubuntu with a Solaris kernel.hailfinger2009-08-172-4/+10
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@686 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Allow the user to override FWH IDSEL on ICH6 and later.hailfinger2009-08-131-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | Usage: flashrom -p internal=fwh_idsel=0 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Log: flashrom v0.9.0-r670 coreboot table found at 0xcf7f3c00. Vendor ID: KONTRON, part ID: 986LCD-M Found chipset "Intel ICH7/ICH7R", enabling flash write... Setting IDSEL=0 for top 8 MBOK. This chipset supports the following protocols: LPC,FWH. Disabling flash write protection for board "Kontron 986LCD-M"... OK. Calibrating delay loop... OK. Found chip "SST SST49LF016C" (2048 KB, FWH) at physical address 0xffe00000. No operations were specified. Acked-by: Chris Kinney <cmkinne@sandia.gov> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Generate the usage message by walking the list of available programmers.hailfinger2009-08-131-3/+32
| | | | | | | | | | | | This makes sure compiled out programmers are not listed. Tested, usage output is identical to the hardcoded variant. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* oops. MSR accesses in board specific code. I missed those.stepan2009-08-121-31/+9
| | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Board enable for Asus P4P800-E Deluxe.libv2009-08-121-0/+27
| | | | | | | | | | | | | Raises what seems to be gpio21. Uses host controller and Promise Raid Controller for a unique match. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Stefan Reinauer <stepan@coresystems.de> Tested-by: Bojan Radakovic <crnibojan@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Allow to compile out serprog completely. If CONFIG_SERPROG is not set,hailfinger2009-08-124-48/+16
| | | | | | | | | | | | | | | | no stubs and no data of serprog will remain. Side benefit: This kills a few dozen lines of code. r678, r679 and r680 made this possible. Once "Only list available programers in usage()" is committed, even the usage message will be adjusted automatically. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use programmer.name to match the --programmer parameter instead ofhailfinger2009-08-122-30/+39
| | | | | | | | | | | | hardcoding the name of every single programmer in main(). -p dummyfoo won't be mistaken for -p dummy anymore. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use a common parameter variable for all programmers. This allows us tohailfinger2009-08-129-62/+54
| | | | | | | | | | | reduce #ifdef clauses a lot if we compile out some programmers completely. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* FT2232 and IT87 programmers used functions of the dummy programmerhailfinger2009-08-123-18/+34
| | | | | | | | | | | | | | | | instead of fallback functions. The dummy programmer is a "real" programmer with possible side effects and its functions should not be abused by other programmers. Make FT2232 and IT87 use official fallback functions instead. Create fallback_shutdown(). Create fallback_chip_writeb(). Convert the programmer #defines to an enum. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix up MSR handling in flashrom to support more OSes than Linux. stepan2009-08-123-70/+156
| | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make debug messages printf_debug(). stepan2009-08-111-15/+15
| | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add ICH6,ICH7,ICH8,ICH9,ICH10 FWH IDSEL settings and flash decodehailfinger2009-08-101-0/+36
| | | | | | | | | | | | settings to the debug output. This can help debug cases where the BIOS does not set up a correct flash decode for the given flash size. The Intel docs state that the decode applies to FWH and SPI flash. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Chris Kinney <cmkinne@sandia.gov> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add IDs for 25 AMD chips, 11 Hynix chips, 8 Sharp chips, and theirhailfinger2009-08-102-22/+65
| | | | | | | | | | | | | | | | | | | variants. AM29DL400BB, AM29DL400BT, AM29DL800BB, AM29DL800BT, AM29F004BB AM29F004BT, AM29F200BB, AM29F200BT, AM29F400BB, AM29F400BT AM29F800BB, AM29F800BT, AM29LV002BB, AM29LV002BT, AM29LV004BB AM29LV004BT, AM29LV008BB, AM29LV008BT, AM29LV080B, AM29LV200BB AM29LV200BT, AM29LV400BB, AM29LV400BT, AM29LV800BB, AM29LV800BT HY29F002, HY29F040A, HY29F080, HY29F400B, HY29F400T, HY29F800B HY29F800T, HY29LV400B, HY29LV400T, HY29LV800B, HY29LV800T LH28F008BJxxPB, LH28F008BJxxPT, LH28F008SA, LH28F008SC, LH28F800BVxxBTL LH28F800BVxxBV, LH28F800BVxxTV, LHF00L02 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Some SPI chip drivers and the generic 1-byte SPI chip write functionshailfinger2009-08-106-47/+30
| | | | | | | | | | | | didn't include the automatic erase present in other chip drivers. Since the majority is definitely auto-erase, change the remaining explicit-erase cases to be auto-erase as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carlos Arnau Perez <cemede@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Releasing IO permissions was done by hand everywhere. Use a properhailfinger2009-08-094-16/+11
| | | | | | | | | | | abstraction. Kill unneeded #include statements. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove unnecessary #include files.hailfinger2009-08-099-18/+3
| | | | | | | | | | | Serprog compilation is now controlled by a Makefile variable. Replace munmap with physunmap where appropriate. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix SPI multicommand endless loop in default_spi_send_multicommand.hailfinger2009-08-031-0/+1
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* The project's new home is flashrom.org now. Change all occurences in thestepan2009-07-304-7/+7
| | | | | | | | | | | source code and documentation accordingly. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Boards with coreboot have a cbtable containing vendor and board name.stepan2009-07-303-2/+12
| | | | | | | | | | | | | | flashrom tries to match these with board enable entries in its database. If no such board enable entry exists because the board doesn't need one, flashrom complains. Silence that complaint. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Slightly updated and Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@668 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add IDs for 51 new flash chips:hailfinger2009-07-242-38/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AMIC A29400T AMIC A29400U AMIC A29800T AMIC A29800U AMIC A29L004T AMIC A29L004U AMIC A29L008T AMIC A29L008U AMIC A29L040 Macronix MX29F004B Macronix MX29F004T Macronix MX29F022T Macronix MX29F080 Macronix MX29F800B Macronix MX29F800T Macronix MX29LV081 Spansion MBM29DL400BC Spansion MBM29DL400TC Spansion MBM29DL800BA Spansion MBM29DL800TA Spansion MBM29F002BC Spansion MBM29F002TC Spansion MBM29F040C Spansion MBM29F080A Spansion MBM29F200BC Spansion MBM29F200TC Spansion MBM29F800BA Spansion MBM29F800TA Spansion MBM29LV002BC Spansion MBM29LV002TC Spansion MBM29LV004BC Spansion MBM29LV004TC Spansion MBM29LV008BA Spansion MBM29LV008TA Spansion MBM29LV080A Spansion MBM29LV200BC Spansion MBM29LV200TC Spansion MBM29LV400BC Spansion MBM29LV400TC Spansion MBM29LV800BA Spansion MBM29LV800TA SST 49LF030A ST M29F080 ST M29F200BB ST M29F200BT ST M29F400BB ST M29F800DB ST M29F800DT Winbond W39L020 Winbond W39L040 Winbond W49F020 These still need to be added to flashchips.c, but if we ever encounter them in real life, the ID->name lookup will be a lot easier. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* If writing failed, verifying is pointless. Abort instead.hailfinger2009-07-241-3/+8
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Oliver Niesner <oli@rhce.servebbs.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Improve flashchip comments to be more readable and precise.hailfinger2009-07-231-5/+14
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Luc Verhaegen <libv@skynet.be> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix erase for SST49LF020A. The chip supports multiple erase functions,hailfinger2009-07-231-1/+1
| | | | | | | | | | but the function we use has an eraseblock size of 4k. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Continue erase/write verification after the first error.hailfinger2009-07-231-6/+13
| | | | | | | | | | | | The first error is printed in detail and all subsequent errors are listed in statistics. This allows users to check if there was just one error or if the failure was widespread. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for old ST M25P05/M25P10 chips which only respond to the REShailfinger2009-07-232-0/+40
| | | | | | | | | | | | | command and not the RDID command. Unfortunately, either the datasheets are wrong or both chips have exactly the same ID. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This is a workaround for a bug in SB600 and SB700. If we only send anhailfinger2009-07-234-28/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | opcode and no additional data/address, the SPI controller will read one byte too few from the chip. Basically, the last byte of the chip response is discarded and will not end up in the FIFO. It is unclear if the CS# line is set high too early as well. That hardware bug is undocumented as of now, but I'm working with AMD to add a detailed description of it to the errata. Add loads of additional debugging to SB600/SB700 init. Add explanatory comments for unintuitive code flow. Thanks go to Uwe for testing quite a few iterations of the patch. Kill the SB600 flash chip status register special case, which was a somewhat misguided workaround for that hardware erratum. Note for future added features in the SB600 SPI driver: It may be possible to read up to 15 bytes of command response with overlapping reads due to the ring buffer design of the FIFO if the command can be repeated without ill effects. Same for skipping up to 7 bytes between command and response. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Verbose probe output is split across multiple lines for some probehailfinger2009-07-233-30/+37
| | | | | | | | | | | | | | | | functions. This makes visual inspection and grepping a lot harder than necessary. Remove line breaks where appropriate. Some error messages should end up on stderr instead of just being displayed in verbose mode. Thanks to Maciej Pijanka for testing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Eliminate version string duplication.hailfinger2009-07-223-2/+4
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert SPI write status register to multicommand infrastructure.hailfinger2009-07-221-26/+24
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Replace most of the switch cases in the spi code with lookup on a structhailfinger2009-07-223-86/+158
| | | | | | | | | | | | | | | | instead. This brings the SPI code in line with the generic programmer infrastructure. This patch is a reworked version of a patch by Jakob Bornecrantz. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Jakob Bornecrantz <wallbraker@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support for an external serial flasher protocol.hailfinger2009-07-212-1/+840
| | | | | | | | | | | | | | | Supports RS-232, USB serial converters (untested) and TCP streams. The protocol specification is in serprog-protocol.txt There will be tweaks to the code and maybe the protocol in the future, so the API is not set in stone yet. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Board enable for Aopen VKM400 AM-S.libv2009-07-211-5/+24
| | | | | | | | | | This board is a VIA KM400 and VT8237 and IT8705F superio. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Scott Johnson <scott@gnuveau.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Reset SST49LF016C after erase to exit the read status register mode.hailfinger2009-07-201-0/+1
| | | | | | | | | | | | | | Without this, all reads after erase will return 0x80 instead of the real memory contents. Thanks to Michael Melcher for testing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Luc Verhaegen <libv@skynet.be> Acked-by: Michael Melcher <Michael.Melcher82@googlemail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use a distinct return code for SPI commands with unsupported/invalidhailfinger2009-07-146-11/+23
| | | | | | | | | | | | | length. Some drivers support only a few combinations of read/write length and return error otherwise. Having a distinct return code for this error means we can handle it in upper layers. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Board enable for Asus A7V8X.libv2009-07-131-0/+39
| | | | | | | | | | | | | GP51 is attached to both WP# and TBL#. Made possible by the quick response of ITE when asked for information, and the tenacious testing of Glenn Mueller. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Glenn Mueller <mechwarrior5@hotmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert SPI byte program to use the multicommand infrastructure.hailfinger2009-07-126-46/+63
| | | | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested it on Epia-m700 worked okay. Acked-by: Jakob Bornecrantz <wallbraker@gmail.com> Tested-by: Jakob Bornecrantz <wallbraker@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert SPI block erase to use the multicommand infrastructure.hailfinger2009-07-111-25/+63
| | | | | | | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Jakob writes: Tested it on my EPIA-m700 and it worked nice. Also double checked that one of the changed functions actually ran. Acked-by: Jakob Bornecrantz <wallbraker@gmail.com> Tested-by: Jakob Bornecrantz <wallbraker@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix incorrect manpage (trivial).uwe2009-07-111-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The flashrom manpage currently says "-w, --write: Write file into flash ROM (default when <file> is specified)". This is no longer true for recent flashrom versions, which only write if you explicitly use the -w option. Proof: $ flashrom coreboot.rom flashrom v0.9.0-r631 No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. Found board "Kontron 986LCD-M", enabling flash write... OK. Calibrating delay loop... OK. Found chip "PMC Pm49FL004" (512 KB) at physical address 0xfff80000. No operations were specified. Thus, fix manpage accordingly. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add Winbond W25X16.hailfinger2009-07-111-0/+16
| | | | | | | | | | | Tested probing and reading only. The chip ID was already in flashchips.h. Signed-off-by: Hector Martin <hector@marcansoft.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert SPI chip erase to use the multicommand infrastructure.hailfinger2009-07-111-18/+62
| | | | | | | | | | | | Once the ICH/VIA SPI driver is converted to multicommand, a lot of hacks can disappear. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Jakob Bornecrantz <wallbraker@gmail.com> Acked-by: Jakob Bornecrantz <wallbraker@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add an optional flash port parameter for IT87* SPI controllers inhailfinger2009-07-114-5/+33
| | | | | | | | | | | | | | standalone programmer mode. If the parameter is set, the IT87* SPI driver will set the I/O base port of the IT87* SPI controller interface to the port specified in the parameter. Usage: flashrom -p it87spi=port=0x820 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@646 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add SPI multicommand infrastructure.hailfinger2009-07-108-42/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some SPI opcodes need to be sent in direct succession after each other without any chip deselect happening in between. A prominent example is WREN (Write Enable) directly before PP (Page Program). Intel calls the first opcode in such a row "preopcode". Right now, we ignore the direct succession requirement completely and it works pretty well because most onboard SPI masters have a timing or heuristics which make the problem disappear. The FT2232 SPI flasher is different. Since it is an external flasher, timing is very different to what we can expect from onboard flashers and this leads to failure at slow speeds. This patch allows any function to submit multiple SPI commands in a stream to any flasher. Support in the individual flashers isn't implemented yet, so there is one generic function which passes the each command in the stream one-by-one to the command functions of the selected SPI flash driver. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Jakob Bornecrantz <wallbraker@gmail.com> Tested-by: Jakob Bornecrantz <wallbraker@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Change tarball compression from gzip to bzip2.hailfinger2009-07-101-5/+10
| | | | | | | | | | | | | | Set the user and group of all files to root for tar versions which support it. Add explanatory comments for supporting that feature with other tar versions. Use LC_ALL instead of LANG everywhere. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* W39V040B: Flag Erase/Write as bad.libv2009-07-081-1/+1
| | | | | | | | | | | | | | | | Chip has now been properly tested in both my Jetway J7F5M and my EPIA-SP (known good board). Erase and write fail. Mark these operations as bad until i or someone else have time to fix this. Reported by Arvid Brodin <arvidb@kth.se>. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> M flashchips.c git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Board enable for Abit IP35.libv2009-07-061-0/+27
| | | | | | | | | | Raise GPIO 16 on ICH9R LPC Interface. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Richie Ward <RichieS@GMail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add more URLs and board notes, fix a typo (trivial).uwe2009-07-042-31/+33
| | | | | | | | | Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Some flashrom printing changes:uwe2009-07-031-9/+20
| | | | | | | | | | | | | | | - Also print URLs of boards with board-enables. - Mark known-bad operations for chips red in the wiki. - Clarifiy a wiki message a bit. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Mark the following boards as working:uwe2009-07-033-17/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - VIA EPIA-M700 (reported by Jakob Bornecrantz <wallbraker@gmail.com>) http://www.coreboot.org/pipermail/coreboot/2009-July/050416.html - GIGABYTE GA-EX58-UD4P (reported by Warren Turkal <wt@penguintechs.org>) http://www.coreboot.org/pipermail/coreboot/2009-June/050199.html Mark as non-working: - ASUS Eee PC 701 4G (reported by Uwe Hermann <uwe@hermann-uwe.de>) There seems to be some SPI flash translation layer, likey done by the embedded controller on the laptop (ENE KB3310). The BIOS chip in this Eee PC model is Winbond 25X40VSIG btw. More info: http://beta.ivancover.com/wiki/index.php/Eee_PC_Research Mark this chip as tested: - ST M25P40 (reported by Jakob Bornecrantz <wallbraker@gmail.com>) http://www.coreboot.org/pipermail/coreboot/2009-July/050416.html Other: - Make the "Albatron PM266A" board detection print "Albatron PM266A*" as this enable will actually work for other PM266A* boards according to libv. However, the code was actually tested on "Albatron PM266A Pro". - Add some more board URLs / notes. - s/BioStar/Biostar/ as per vendor website. - Fix typo in print.c: s/A7V8-MX SE/A7V8X-MX SE/. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ft2232_spi: Allow runtime selection of FT2232H vs. FT4232H andhailfinger2009-07-014-9/+66
| | | | | | | | | | | interface A vs. B. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Jakob Bornecrantz <wallbraker@gmail.com> Acked-by: Jakob Bornecrantz <wallbraker@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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