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* Tag flashrom 0.9.5.2flashrom-0.9.5.2hailfinger2012-03-080-0/+0
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/tags/flashrom-0.9.5.2@1515 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Increase flashrom release number to 0.9.5.2hailfinger2012-03-081-1/+1
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Prevent submission of empty read requests in linux_spi.mkarcher2012-03-061-2/+14
| | | | | | | | | | | | | | The submission of zero-sized read requests in a write-only transaction fails at least for omap2_mcspi drivers and is pointless in general. This patch does not address the implementation of zero-sized writes (which would need to skip the write command), as there are no flash transactions not starting with a command. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* linux_spi.c: set SPI mode, bit order and bits per word on init.stefanct2012-03-031-3/+19
| | | | | | | | | | | | | | Previously we relied on a correctly set up state. Also, we start to rely on the shutdown function for cleanup after registering it, i.e. we no longer explicitly call close(fd) after register_shutdown(). Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Tested-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix parallel-style programmer access from ITE IT87/Winbond W83627 SPIhailfinger2012-03-015-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | The ITE IT87 SPI driver uses a trick to speed up reading and writing: If a flash chip is 512 kByte or less, the flash chip can be completely mapped in memory and both read and write accesses are faster that way. The current IT87 SPI code did use the parallel programmer interface for memory mapped reads and writes, but that's the wrong abstraction. It has been fixed to use mmio_read*/mmio_write* for that purpose. The Winbond W83627 SPI driver uses the same trick in its read path for all supported chip sizes. Fix it the same way. Switch internal_chip_readn to use mmio_readn as proper abstraction. Kudos to Michael Karcher for spotting the bugs. Reported-by: Johan Svensson <flashrom.js@crypt.se> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Tested-by: Johan Svensson <flashrom.js@crypt.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* nicintel_spi.c: check if write enable is really set (and minor comment changes).stefanct2012-02-271-3/+14
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Increase flashrom release number to 0.9.5.1hailfinger2012-02-251-1/+1
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1508 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support Debian/kFreeBSDhailfinger2012-02-254-7/+14
| | | | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Robert Millan <rmh@debian.org> Tested-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* SFDP: Fetch parameter table in a more portable wayhailfinger2012-02-241-7/+16
| | | | | | | | | | | | | | SFDP parameter table reads expect a dummy byte between written data (opcode+address) and read data on the SPI bus. Read that dummy byte instead of writing it to be compatible with all programmer drivers. Reduce SFDP parameter table read chunk size from 8 to 2 to handle programmers with small readcount limits. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix SFDP probing.stefanct2012-02-221-26/+39
| | | | | | | | | | | | | | | | | | | | | | sfdp_add_uniform_eraser checks for existing erasers. Due to a bug it looked for eraser slots that have no erase functions set instead of those that have one set. Postpone adding an erase function for the special 4k block erase opcode until we know the flash chip size and add an additional check to sfdp_add_uniform_eraser. Fix the output of the parameter table contents. This patch fixes the index used to retrieve the eraser types, which was off one double word. Refine some messages and add a few further debugging prints. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Increase flashrom release number to 0.9.5hailfinger2012-02-181-1/+1
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1503 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 11stefanct2012-02-173-1/+4
| | | | | | | | | | | | | | | Tested Mainboards: NOT OK: - HP dc7800 http://paste.flashrom.org/view.php?id=1084 - add "Low Profile Desktop" to our dmi whitelist - fix print_wiki (broken since r1488) Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for ASUS OPLX-M.stefanct2012-02-172-0/+3
| | | | | | | | | | | | | | | | | The vendor enable does some other funky stuff with MTRRs/MSRs, SMIs, cache and legacy ISA address forward twiddling. I would only use this patch to read and verify the existing contents, just to be safe. The PCI IDs of the onboard devices do contain no subsystem IDs at all. Probing and reading was Tested-by: Ville Skyttä <ville.skytta@iki.fi> See http://www.flashrom.org/pipermail/flashrom/2010-October/005256.html Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for SFDP (JESD216).stefanct2012-02-179-12/+467
| | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to modules using the opaque programmer framework (e.g. ICH Hardware Sequencing) this uses a template struct flashchip element in flashchips.c with a special probe function that fills the obtained values into that struct. This allows yet unknown SPI chips to be supported (read, erase, write) almost as if it was already added to flashchips.c. Documentation used: http://www.jedec.org/standards-documents/docs/jesd216 (2011-04) W25Q32BV data sheet Revision F (2011-04-01) EN25QH16 data sheet Revision F (2011-06-01) MX25L6436E data sheet Revision 1.8 (2011-12-26) Tested-by: David Hendricks <dhendrix@google.com> on W25Q64CV + dediprog Tested-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> on a 2010 MX25L6436E with preliminary (i.e. incorrect) SFDP implementation + serprog Thanks also to Michael Karcher for his comments and preliminary review! Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 10stefanct2012-02-168-29/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ABIT A-S78H http://www.flashrom.org/pipermail/flashrom/2012-January/008603.html - ASRock AM2NF6G-VSTA http://www.flashrom.org/pipermail/flashrom/2012-January/008534.html - ASUS KFSN4-DRE/SAS reported by ted on IRC - ASUS M2A-VM (HDMI variant) http://www.flashrom.org/pipermail/flashrom/2012-January/008509.html - ASUS M4N78 PRO http://www.flashrom.org/pipermail/flashrom/2012-January/008598.html - ASUS P5K-V http://www.flashrom.org/pipermail/flashrom/2012-February/008737.html - ASUS P5KPL-CM http://www.flashrom.org/pipermail/flashrom/2012-January/008522.html - ASUS P5N7A-VM http://www.flashrom.org/pipermail/flashrom/2012-January/008508.html - ASUS P5QPL-AM http://www.flashrom.org/pipermail/flashrom/2012-January/008557.html - ECS GF7100PVT-M3 http://www.flashrom.org/pipermail/flashrom/2011-December/008412.html - ECS K7SEM http://www.flashrom.org/pipermail/flashrom/2011-December/008362.html - ECS P4M800PRO-M V2.0 http://www.flashrom.org/pipermail/flashrom/2012-January/008478.html - Gigabyte 880GMA-USB3 http://www.flashrom.org/pipermail/flashrom/2012-February/008715.html - Gigabyte GA-EP31-DS3L http://www.flashrom.org/pipermail/flashrom/2012-January/008601.html - Gigabyte GA-X58A-UDR3 http://www.flashrom.org/pipermail/flashrom/2012-January/008572.html - Gigabyte GA-Z68XP-UD3 http://paste.flashrom.org/view.php?id=1058 - HP ProLiant N40L http://www.flashrom.org/pipermail/flashrom/2012-February/008650.html - MSI MS-7309 (K9N6PGM2-V2) http://www.flashrom.org/pipermail/flashrom/2011-December/008441.html - MSI MS-7548 (Aspen-GL8E used in HP Pavilion a6750f) http://www.flashrom.org/pipermail/flashrom/2012-February/008666.html - MSI MS-7676 (H67MA-ED55(B3)) http://www.flashrom.org/pipermail/flashrom/2012-January/008547.html - PC Engines Alix.6f2 Reported by Philip Prindeville on IRC - Shuttle AV18E2 http://www.flashrom.org/pipermail/flashrom/2011-December/008459.html - Supermicro X8DTE-F http://www.flashrom.org/pipermail/flashrom/2011-November/008304.html - Supermicro X8DTT-HIBQF http://www.flashrom.org/pipermail/flashrom/2012-January/008520.html NOT OK: - ASUS P8H61-M LE/USB3 http://www.flashrom.org/pipermail/flashrom/2012-January/008491.html - ASUS P8H67-M PRO http://www.flashrom.org/pipermail/flashrom/2011-December/008321.html - ASUS P8Z68-V PRO http://www.flashrom.org/pipermail/flashrom/2012-January/008469.html - Clevo P150HM (laptop) http://www.flashrom.org/pipermail/flashrom/2012-February/008717.html - Intel D425KT http://www.flashrom.org/pipermail/flashrom/2012-January/008600.html - Supermicro X9SCA-F http://www.flashrom.org/pipermail/flashrom/2011-December/008313.html Tested flash chips: - mark AT29C512 as TEST_OK_PREW http://paste.flashrom.org/view.php?id=977 - mark M25P40 as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-December/008351.html - mark M25PE80 as TEST_OK_PREW http://paste.flashrom.org/view.php?id=1061 - mark MX25L6405 as TEST_OK_PREW tested myself with an MX25L6436E variant on serprog - mark W39V080A as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2012-January/008509.html Tested chipsets: - SiS 730 (:0730) http://www.flashrom.org/pipermail/flashrom/2011-December/008362.html - NVIDIA MCP61 (:03e0) http://www.flashrom.org/pipermail/flashrom/2012-January/008534.html - NVIDIA MCP73 (:07d7) http://www.flashrom.org/pipermail/flashrom/2011-December/008412.html - NVIDIA MCP79 (:0aac) http://www.flashrom.org/pipermail/flashrom/2012-January/008508.html - VIA VT82C69x (0691) and VT82C686A/B (:0686) http://www.flashrom.org/pipermail/flashrom/2011-December/008459.html - AMD's SB950 (and presumably also SB920) have the same PCI ID as previous generations, hence change the chipset enable device string. Thanks to Christian Ruppert for the suggestion. - Fix the board enable of the abit NF-M2 nView which had the IDs of its onboard graphics card in its pattern. Change this to the LPC controller. - Intel X79 SPI registers are identical to 6 Series', so use the chipsetenable wrapper of it (enable_flash_pch6). - Fix two paranoid checks for address < 0 in ichspi.c which became futile (and generate clang warnings) with the unsignify patch committed in r1470. - Rename AT25DF641 to AT25DF641(A). They are almost idencical, but could be distinguished by an extended RDID probe (Atmel's patented EDI procedure), which we do not support yet, hence handle them as one model for now. - Source format fixes and typos the addition of the ASRock AM2NF6G-VSTA to print.c is Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> everything else is Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Document and enable the linux_spi driverhailfinger2012-02-163-9/+34
| | | | | | | | | | | The linux_spi driver is now enabled by default on Linux. A man page entry and a line in --list-supported output have been added. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Manpage improvements.stefanct2012-02-161-34/+77
| | | | | | | | | | | | | | | | | | | | | The sections describing the various options of the internal and dummy programmers have grown out of proportions. This patch adds some headlines to devide the unrelated topics a bit (with .TP commands). The previous indented paragraphs for the various programmers were transformed to subsections (.SS). Also, rephrase the documention related to laptops completely to make it less redundant and more informative. Document the laptop=this_is_not_a_laptop internal programmer parameter Change the contact info in the bugs section by removing the trac reference and adding IRC (and the pastebin) instead. Remove some superfluous white space and a .RE (restore indentation) command. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Reenable forced readhailfinger2012-02-161-4/+19
| | | | | | | | | | | | | | | | | | | | | Forced read functionality was disabled when programmer registration was merged in r1475. We now support registering more than one controller at once for each bus type. This can happen e.g. if one SPI controller has an attached flash chip and one controller doesn't. In such a case we rely on the probe mechanism to find exactly one chip, and the probe mechanism will remember which controller/bus the flash chip is attached to. A forced read does not have the luxury of knowing which compatible controller to use, so this case is handled by always picking the first one. That may or may not be the correct one, but there is no way (yet) to specify which controller a flash chip is attached to. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Workaround missing %hhx support in MinGW sscanfhailfinger2012-02-161-2/+12
| | | | | | | | | | | MinGW uses standard Windows C libraries and those apparently don't support %hhx for sscanf into a uint8_t. SCNx8 isn't available either. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi.c: warn user and disable writes when a protected address range is ↵stefanct2012-02-162-25/+89
| | | | | | | | | | | | | | | detected. This includes not only the notorious read-only flash descriptors and locked ME regions, but also the more rarely used PRs (Protected Ranges). The user can enforce write support by specifying ich_spi_force=yes in the programmer options, but we don't tell him the exact syntax interactively. He has to read it up in the man page. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Warn of one-time programmable (OTP) memorystefanct2012-02-154-28/+62
| | | | | | | | | | | | | | | | | | Some flash chips contain OTP memory that we cannot read or write (yet). This prohibits us from cloning them, hence warn the user if we detect it. Not all variations of the tagged chips contain OTP memory. They are often only enabled on request or have there own ordering numbers. There is usually no way to distinguish them. Because this is a supposedly seldomly used feature the warning is shown in with dbg verbosity. The manpage is extended to describe the backgrounds a bit. This patch is based on the idea and code of Daniel Lenski. Signed-off-by: Daniel Lenski <dlenski@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support compilation for the ARM architecture (little-endian only).hailfinger2012-02-135-3/+31
| | | | | | | | | | | | | | Note: The internal programmer will abort during processor check. This is intentional. The other hardware drivers (except those using port I/O) should work. Signed-off-by: David Hendricks <dhendrix@google.com> Acked-by: David Hendricks <dhendrix@google.com> Tested-by: Timo Juhani Lindfors <timo.lindfors@iki.fi> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1492 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Board enable for TriGem Anaheim-3mkarcher2012-02-122-0/+3
| | | | | | | | | | | | lspci: http://paste.flashrom.org/view.php?id=1069 flashrom -V: http://paste.flashrom.org/view.php?id=1072 flashrom -w: http://paste.flashrom.org/view.php?id=1073 Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> (ack via IRC Feb 11, 23:14 GMT) git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1491 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* SPI command black-/ignorelisting for the flash chip emulator in the dummy ↵hailfinger2012-02-082-3/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | programmer Usage: flashrom -p dummy:spi_blacklist=commandlist flashrom -p dummy:spi_ignorelist=commandlist If commandlist is 0302, flashrom will refuse (blacklist) or ignore (ignorelist) command 0x03 (READ) and command 0x02 (WRITE). The commandlist can be up to 512 bytes (256 commands) long. Specifying flash chip emulation is a good idea to get useful results. Very useful for testing corner cases if you don't own a locked down Intel chipset and want to simulate such a thing. Example usage: dd if=/dev/zeros bs=1024k count=4 of=dummy_simulator.rom dd if=/dev/urandom bs=1024k count=4 of=randomimage.rom flashrom -p dummy:emulate=SST25VF032B,image=dummy_simulator.rom,\ spi_blacklist=20,spi_ignorelist=52 -w randomimage.rom -V Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for RDC R6030 chipsetstefanct2012-02-072-0/+28
| | | | | | | | | Tested on Bifferboard. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1489 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* print*.c: Refine the do not count nor print generic flash chip entries ↵stefanct2012-02-032-9/+16
| | | | | | | | | | | | | | | | | | conditions. Previously only the generic "unknown XXXX SPI chips" were ignored (because their name started with "unknown". This patch adds also all chips whose vendor starts with "Unknown" (none so far) and "Programmer" (currently used by the opaque flash chip framework) . A patch will add the SFDP chip template with an "Unknown" vendor field later. Rationale: these entries do not contain any useful information when shown in -L or wiki output. It would be better to add them to a general feature section or similar. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for the MSC Q7 Tunnel Creek boardstefanct2012-01-312-0/+15
| | | | | | | | | | | This patch adds a generic phase 2 board enable that does nothing but set is_laptop to 0 to circumvent an erroneous laptop detection due to ambigous DMI chassis information. Signed-off-by: Ingo Feldschmid <ifel@msc-ge.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for AOpen i945GMx-VFX (used in FCS ESPRIMO Q5010)stefanct2012-01-192-0/+12
| | | | | | | | | | | | | | Typical AWARD enable structure with an ICH GPIO board enable. This board seems also to be known as D2544-B1. Success report: http://www.flashrom.org/pipermail/flashrom/2012-January/008590.html Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Tested-by: Oliver Rath <rath@mglug.de> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Reorder list of options to testhailfinger2012-01-121-1/+1
| | | | | | | | | | | | | | | | | | If a chip is unknown the user is asked to test and report the result to the mailing list. Having `-VE` listed as the last option can result in an unbootable system for users not knowing what the command does, since rebooting the system after that command is fatal since the flash chip is empty. Example report at http://www.flashrom.org/pipermail/flashrom/2012-January/008551.html Reorder the options to prevent such accidents in the future. Suggested by Idwer Vollering. Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Postpone layout file readinghailfinger2012-01-111-6/+12
| | | | | | | | | | | | | | Layout file reading should happen after option parsing like all other file accesses. Guard against multiple --layout parameters. Followup fix for r1483: Remove -m short option from getopt. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1484 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Replace --mainboard with -p internal:mainboardhailfinger2012-01-049-67/+62
| | | | | | | | | | | | | | | | | | | | | | | | | --mainboard is a relic from a time before external programmers and makes the CLI inconsistent. Use a programmer parameter instead and free up the short option -m. NOTE: The --list-supported-wiki output changed to use -p internal:mainboard= instead of -m The --list-supported output changed the heading of the mainboard list from Vendor Board Status Required option to Vendor Board Status Required value for -p internal:mainboard= Fix lb_vendor_dev_from_string() not to write to the supplied string. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add deferred --image processingstefanct2011-12-253-20/+78
| | | | | | | | | | | | | | | | | | | | | | | The general idea and most of the code are based on the following commits in the chromiumos flashrom tree: 8fc0740356ca15d02fb1c65ab43b10844f148c3b bb9049c66ca55e0dc621dd2c70b5d2cb6e5179bf Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> and the main part: d0ea9ed71e7f86bb8e8db2ca7c32a96de25343d8 Signed-off-by: David Hendricks <dhendrix@chromium.org> This implementation does not defer the processing until doit(), but after the argument parsing loop only (doit() should not contain argument checks). This allows to specify -i and -l parameters in any order. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* layout: change return type and name of find_next_included_romentrystefanct2011-12-251-16/+17
| | | | | | | | | | | | | - rename from find_next_included_romentry to get_next_included_romentry - return a pointer to a rom_entry instead of just its index. this relieves the (single existing) caller from directly accessing the data structure holding the entries hence improving segregation and readability. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add ich_descriptor_tool to decode all flash descriptors stored in a flash ↵stefanct2011-12-246-2/+1135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | dump file This patch adds an external utility that shares most of the existing descriptor decoding source code. Additionally to what is available via FDOC/FDOD this allows to access: - the softstraps which are used to configure the chipset by flash content without the need for BIOS routines. on ICH8 it is possible to read those with FDOC/FDOC too, but this was removed in later chipsets. - the ME VSCC (Vendor Specific Component Capabilities) table. simply put, this is an SPI chip database used to figure out the flash's capabilities. - the MAC address stored in the GbE image. Intel thinks this information should be confidential for ICH9 and up, but references some tidbits in their public documentation. This patch includes the human-readable information for ICH8, Ibex Peak (5 series) and Cougar Point (6 series); the latter two were obtained from leaked "SPI Flash Programming Guides" found by google. Data regarding ICH9 and 10 is unknown to us yet. It can probably found in: "Intel® ICH7, ICH8, ICH9 and ICH10 — SPI Family Flash Programming Guide" Information regarding the upcoming Panther Point chipset is also not included. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Matthias Wenzel <bios@mazzoo.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix programmer-centric probe (patch v2)mkarcher2011-12-221-2/+3
| | | | | | | | | | | | | | | As reported by Stefan Tauner on IRC, the new programmer-centric logic is broken by re-using occupied members of the flashes array when changing to the next programmer. This fixes it. patch v2: prevent probing one chip per programmer even if the array is full. Using a do-while loop was a bad idea. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ft2232_spi: fix arm-usb-ocd and arm-usb-ocd-hhailfinger2011-12-201-0/+4
| | | | | | | | | | | | | These devices have an additional output buffer which is activated only by pulling ADBUS4 low. This patch was real-life tested with arm-usb-ocd; arm-usb-ocd-h should be the same (as it shares the same documentation). Signed-off-by: Paul Fertser <fercerpav@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Speed up dediprog SPI page writeshailfinger2011-12-201-6/+170
| | | | | | | | | | | | | | | All chips which use spi_chip_write_256 should be written at native speed. Chips using spi_chip_write_1 or spi_chip_write_aai will still be slow. Thanks to Steven A. Falco for testing with a ST/Numonyx M25P16. Thanks to David Hendricks for testing with a Winbond W25Q64. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Steven A. Falco <sfalco@coincident.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Cross-compilation fixeshailfinger2011-12-202-25/+100
| | | | | | | | | | | | | | | | | | | | | | | Switch from host OS detection to target OS detection. Complain about unknown target OS/architecture. Disable annoying format string warnings on DJGPP. Native and cross-compilation now usually just require setting CC. Examples: make CC=i586-pc-msdosdjgpp-gcc make CC="clang -m64" make CC=i686-w64-mingw32-gcc Tested for a boatload of native and cross compilation configurations. There is a new target "make libpayload" in case you don't want to specify all tools by hand. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Have all programmer init functions register bus masters/programmershailfinger2011-12-2014-251/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | All programmer types (Parallel, SPI, Opaque) now register themselves into a generic programmer list and probing is now programmer-centric instead of chip-centric. Registering multiple SPI/... masters at the same time is now possible without any problems. Handling multiple flash chips is still unchanged, but now we have the infrastructure to deal with "dual BIOS" and "one flash behind southbridge and one flash behind EC" sanely. A nice side effect is that this patch kills quite a few global variables and improves the situation for libflashrom. Hint for developers: struct {spi,par,opaque}_programmer now have a void *data pointer to store any additional programmer-specific data, e.g. hardware configuration info. Note: flashrom -f -c FOO -r forced_read.bin does not work anymore. We have to find an architecturally clean way to solve this. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add struct flashctx * parameter to all functions accessing flash chips.hailfinger2011-12-1842-541/+727
| | | | | | | | | | | | | | | | | All programmer access function prototypes except init have been made static and moved to the respective file. A few internal functions in flash chip drivers had chipaddr parameters which are no longer needed. The lines touched by flashctx changes have been adjusted to 80 columns except in header files. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use struct flashctx instead of struct flashchip for flash chip accesshailfinger2011-12-1429-269/+301
| | | | | | | | | | | | | | | | | | | | | | | struct flashchip is used only for the flashchips array and for operations which do not access hardware, e.g. printing a list of supported flash chips. struct flashctx (flash context) contains all data available in struct flashchip, but it also contains runtime information like mapping addresses. struct flashctx is expected to grow additional members over time, a prime candidate being programmer info. struct flashctx contains all of struct flashchip with identical member layout, but struct flashctx has additional members at the end. The separation between struct flashchip/flashctx shrinks the memory requirement of the big flashchips array and allows future extension of flashctx without having to worry about bloat. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Update URLs in print.chailfinger2011-12-081-72/+72
| | | | | | | | | | | Move Asus A8Jm, Asus M6Ne to the laptop section. No working URL for the A8Jm found. Signed-off-by: Benjamin Bellec <b.bellec@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 9stefanct2011-12-022-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ABIT NF-M2S http://www.flashrom.org/pipermail/flashrom/2011-October/008155.html - ASUS P5K-VM http://www.flashrom.org/pipermail/flashrom/2011-October/008172.html - ASUS M5A99X EVO http://www.flashrom.org/pipermail/flashrom/2011-October/008152.html - ASUS Z8PE-D12 http://www.flashrom.org/pipermail/flashrom/2011-November/008195.html - PC Engines Alix.2d3 http://www.flashrom.org/pipermail/flashrom/2011-November/008244.html NOT OK: - ASUS P8H61 PRO http://www.flashrom.org/pipermail/flashrom/2011-November/008308.html - ASUS P8P67 (rev. 3.1) http://www.flashrom.org/pipermail/flashrom/2011-November/008292.html - MSI MS-7613 (Iona-GL8E) http://www.flashrom.org/pipermail/flashrom/2011-November/008295.html - MSI MS-7635 (H55M-ED55) http://www.flashrom.org/pipermail/flashrom/2011-October/008167.html - Supermicro X9SCL http://www.flashrom.org/pipermail/flashrom/2011-November/008254.html - ZOTAC H67-ITX WiFi http://paste.flashrom.org/view.php?id=902 Tested flash chips: - mark Pm29F002T as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-October/008171.html - mark AMIC A49LF040A as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-November/008244.html - mark Winbond W39V040FC as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-November/008281.html - source format fixes Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unsignify lengths and addresses in chip functions and structsstefanct2011-11-2322-143/+150
| | | | | | | | | | Push those changes forward where needed to prevent new sign conversion warnings where possible. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for ASUS A7N8X-VM/400stefanct2011-11-192-0/+11
| | | | | | | | | http://www.flashrom.org/pipermail/flashrom/2011-November/008274.html Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for ASRock ConRoeXFire-eSATA2stefanct2011-11-162-0/+2
| | | | | | | | | | | | | | The reverse engineering was done by Joshua. The actual patch was fabricated by Paul with some polishing by Stefan. Success log: http://www.flashrom.org/pipermail/flashrom/2011-November/008257.html Signed-off-by: Joshua Roys <roysjosh at gmail.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for ASUS P4GV-LA (Guppy)stefanct2011-11-152-0/+2
| | | | | | | | | | | | | | | | | The reverse engineering was done by Joshua. The actual patch was fabricated by Stefan. Request: http://www.flashrom.org/pipermail/flashrom/2011-November/008241.html Success report: http://paste.flashrom.org/view.php?id=914 Signed-off-by: Joshua Roys <roysjosh@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Tested-by: Mugendai <mugendai42@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* board_enable.c: Make it8712f_gpio_set genericstefanct2011-11-142-31/+81
| | | | | | | | | | | | | | | This looks suspiciously like intel_ich_gpio_set. Based on that, add board enables for the ASUS P5N-D and P5N-E SLI. This was tested by Guillaume Poirier-Morency on a P5N-D: http://www.flashrom.org/pipermail/flashrom/2011-August/007706.html Signed-off-by: Joshua Roys <roysjosh@gmail.com> Small changes were also contributed and Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Create a directory for documentation filesstefanct2011-11-132-0/+18
| | | | | | | | | | Move the serprog specification there and document a few things we could not figure out on intel platforms yet. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: fix ich_init_opcodes() calls in ich_init_spi()stefanct2011-11-131-2/+2
| | | | | | | | | | | | | | By calling it early ichspi_lock was not set up correctly in accordance with the corresponding register, hence ich_init_opcodes() was always trying to programming the opcodes instead of reading them in from the opmenu in case of a locked down configuration. Thanks to Jonathan A. Kollasch for reporting this bug. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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