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* sbxxx: Set SPI clock to 16.5 MHz and disable fast reads.stefanct2013-09-151-8/+63
| | | | | | | | | | | | | | Do not rely on broken firmware to set up the SPI configuration correctly. Some boards fail with flashrom because the firmware chose too high speeds for the alternate SPI mode which flashrom uses. Temporarily change the clock to the lowest common value of 16.5 MHz. Also, disable fast reads just to be safe. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* layout: Add a method to cleanup layout data structures.stefanct2013-09-153-2/+18
| | | | | | | | | Add layout_cleanup() to layout.c and hook it up in cli_classic.c. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Enable fwh_idsel parameter for C-ICH and ICH2/3/4/5 chipsets.stefanct2013-09-142-13/+23
| | | | | | | | | | Register locations are different from ICH6, but otherwise appear to have identical bit specifications and defaults. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use ich_generation parameter in enable functions prior to ICH7.stefanct2013-09-142-25/+64
| | | | | | | | | | | Follow the style used from ICH7 onwards to pass ich_generation parameter to lower-level functions on older ICH chipsets too. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce enable_flash_ich_fwh_decode().stefanct2013-09-141-8/+28
| | | | | | | | | | | | | | | | ICH2 (and C-ICH)/3/4/5 also have FWH_SEL1/2 registers but at different addresses. In preparation for implementing fwh_idsel parsing for older ICH chipsets extract the parameter handling and add variables for the offsets. While FWH_DEC_EN1 is a 16bit register for ICH6, it is two separate 8bit registers on ICH5 and earlier. Implement all accesses with two byte instructions instead, to prepare for extended support. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove exit call and mayfail parameter from physmap_common().stefanct2013-09-147-28/+25
| | | | | | | | | | | | | | | The only call path where exit was reached was from physmap functions. Callers of physmap() et al. which were not prepared to handle ERROR_PTR return values have been adjusted. physmap_try_ro() has been renamed to physmap_ro() and physmap_common() slightly refactored due to the now removed *FAIL parameters. Signed-off-by: Niklas Söderlund <niso@kth.se> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove exit call from sys_physmap_*.stefanct2013-09-132-9/+6
| | | | | | | | | | All callers are prepared to handle error if ERROR_PTR is returned. The Manpage mentioning the respective return code is readapted. Signed-off-by: Niklas Söderlund <niso@kth.se> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add debug output to programmer_map_flash_region().stefanct2013-09-131-2/+4
| | | | | | | | | | While we don't expect addresses with more than 32 bits here, let's print the whole possible range for debugging anyway. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* BSD refinements.stefanct2013-09-124-10/+56
| | | | | | | | | | | | | | | Make it easier to compile flashrom under NetBSD and DragonFlyBSD: - Use /usr/pkg/ as prefix for includes and linking - Use pciutils as include path for the right(tm) libpci Also, fix date handling in getrevision.sh to work with the various formats for invoking 'date'. This also uses svn's info --xml output instead of the regular one. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Tested-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* sbxxx: Add detection for the remaining AMD chipset families.stefanct2013-09-121-27/+110
| | | | | | | | | | | | | Also, correct prettyprinting of the registers of the various families, and abort if SpiAccessMacRomEn or SpiHostAccessRomEn prohibit full access. Tested reading/writing on ASRock IMB-A180, and chipset detection on one of each affected generation by Chris Goodrich from Sage. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Makefile: Warn if user tries to compile for libpayload w/o crossgcc.stefanct2013-09-121-0/+5
| | | | | | | | | | | | While flashrom is not as picky on compilers as coreboot, there is still a high probablilty of breakage when one combines libpayload and distribution compilers. Print a warning if we detect that to give the daring user a hint how to resolve the explosions potentially following below it. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix ROM decoding on VIA VT82C596 and VT82C686A/B.stefanct2013-09-121-13/+43
| | | | | | | | | | | | | | These support an additional bit which we did not turn on yet. Without this patch they decode up to 512 kB, with this up to 1 MB. Disentangle the enables of unrelated but mostly compatible chipsets too, add some more debug output and set the max_rom_decode limits. Also, make warnings really only warnings. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Enable sector erase function for selected ST M50 chips.stefanct2013-09-122-10/+22
| | | | | | | | | Affected chips: M50FLW040A, M50FLW040B, M50FLW080A, M50FLW080B. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for ST M50LPW080.stefanct2013-09-122-0/+26
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Cleanup ST M50 driver.stefanct2013-09-126-137/+127
| | | | | | | | | | | | | | | There are two locking strategies used by this umbrella family, one uniform and one that matches the sector layout of the chip. Refactor the functions involved and rename the overly complicated file to just stm50.c and the functions accordingly. This fixes unlocking of some of the non-uniform chips and gets rid of the abuse of page_size. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add an internal DMI decoder.stefanct2013-09-115-63/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we had to rely on dmidecode to decode the DMI/SMBIOS table. This patch integrates a DMI decoder into flashrom. The old behavior of calling dmidecode can be brought back by using CONFIG_INTERNAL_DMI=no. Significant portions of this patch were taken from dmidecode, hence add its authors to the copyright notice (dmidecode is also GPL2+). We do a few things differently though. First of all we do more bounds checking to prevent accessing unmapped memory. We do not support disovery via EFI (yet), but memory scanning only. We handle the chassis-type lock bit correctly which dmidecode did not for a long while. The API to the rest of flashrom remains stable, but the output changes slightly. To share as much code as possible (which actually is not much), i have added dmi_fill methods that get called in dmi_init. They are reponsible to fill the dmi_strings array and setting the is_laptop variable. After it is called, dmi_init prints all dmi_strings. Previously the strings were printed in the order they were discovered, followed by the chassis-type, which is now output earlier (in dmi_fill). Because DJGPP does not support strnlen a simple implementation was added for it. This is still only available on x86; actually it is not even compiled in for other architectures at all anymore. Signed-off-by: Sean Nelson<audiohacked@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Tested-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* DOS refinements.stefanct2013-09-112-13/+19
| | | | | | | | | | | | | This allows to use the DOS library trees stored in a user-specified directory. I have mirrored the needed patches, sources and binaries (the latter are properly licensed to allow that) in the flashrom wiki, so use those URLs instead of the original sources. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for Bcom WinNET P680.stefanct2013-09-102-1/+2
| | | | | | | | | | | | | This patch replaces Alex Mauer's previous patch for this board (from 2008). Tested to read, erase, and write on 2 different boards, both with AMIC A29040BL flash chips, using both stock BIOS and coreboot images. This patch marks the AMIC chip as tested at the same time. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* layout: Rename romlayout_t to romentry_t.stefanct2013-08-301-6/+6
| | | | | | | | | | | | The type describes one entry of the whole layout actually. Using layout_entry_t or something similar would be more correct, but due to it length we will use "rom" instead of "layout" here and in upcoming code. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* layout: Rename romimages to num_rom_entries.stefanct2013-08-301-19/+18
| | | | | | | | | | | | Since we are planning to support image files for rom entries, rename the variable used to count the number of known rom entries to avoid confusion. There is already num_include_args with similar semantics, hence we use num_rom_entries. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* libpayload: Remove file I/O in flashrom.c.stefanct2013-08-301-0/+10
| | | | | | | | | | | read_buf_from_file() and write_buf_to_file() use file streams which are not supported in libpayload. Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add now auto-generated manpage to svn:ignore.stefanct2013-08-290-0/+0
| | | | | | | | | | I had to touch svn directly, where is my reimbursement? Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Automatically add version and date to the manpage.stefanct2013-08-292-6/+10
| | | | | | | | | | | | To avoid funny effects of ever changing files tracked by the VCS this patch moves the manpage data to flashrom.8.tmpl and generates the actual manpage with a new makefile target if needed. Signed-Off-By: Joerg Mayer <jmayer@loplof.de> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Improve getrevision.sh.stefanct2013-08-292-151/+203
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | - remove bashism. - simplify some git-related code. - improved parameter and error handling. - additional -d/--date action which is similar to the timestamp action. - support for an optional path parameter. - there is only one sane time format. - and only one sane date format too. - use UTC dates and times only. - vastly improve git_url() to print the correct remote url and "nearest" branch. - remove username from repository URLs. - add "-dirty" to local revisions if there are uncommitted changes. - indicate in local revisions how many git-only commits were done since branching from upstream svn. - fix svn_revision() fallback to svn info and remove git-svn. - print leading r in script instead of hardcode it in the makefile; no more "0.9.7-runknown". - make retrieving the upstream revision work even in cloned git-svn repositories. - more abstractions and helper functions. - less fragmentation of actual functionality. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* libpayload: By default build libflashrom.a instead of flashrom.stefanct2013-08-281-0/+4
| | | | | | | | | | | | | | | | | | | | | flashrom won't build nor run as native payload very soon (or ever). This patch changes a special GNU make variable that allows to select the default goal which is taken if no goal is given explicitly on the command line. Normally this would be the first rule in Makefile, i.e. all. This won't compile if the target OS is libpayload, hence change it to "libflashrom.a" in that case. This requires two not completely ancient GNU make features: - MAKECMDGOALS - .DEFAULT_GOAL Checking for these with ancient-only GNU make features is non-trivial and hereby postponed. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for AT45CS1282.stefanct2013-08-273-3/+60
| | | | | | | | | | | This one is even more strange than the AT45DB chips. Like the AT45DB321C it does not support any power-of-2 page sizes. There is only one asymmetrical eraser and that uses two opcodes. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for AT45DB321C.stefanct2013-08-273-6/+81
| | | | | | | | | | It seems like this model is one-of-a-kind... it shares some properties with the older versions of the AT45DB series as well as with new ones. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Atmel AT45DB* chips.stefanct2013-08-277-59/+759
| | | | | | | | Signed-off-by: Aidan Thornton <makosoft@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Fujitsu MBM29LV160BE/TE.stefanct2013-08-252-0/+66
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Makefile: Explain process of handling CONFIG_* variables.stefanct2013-08-251-2/+13
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* IT87: Add ability to select between chips on GIGABYTE DualBIOS boards.stefanct2013-08-243-10/+55
| | | | | | | | | | | | | | | Thanks to Vadim Girlin for finding out how to do that. This is known to work on GA-MA770-UD3, GA-B75M-D3V, GA-B75N and GA-H61M-S1 (only M_BIOS is populated). Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Tested-by: Damien Zammit <damien@zamaudio.com> Tested-by: Anton Kochkov <anton.kochkov@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Get rid of sp_die().stefanct2013-08-243-63/+99
| | | | | | | | | | | | | | - Add return values to sp_flush_stream(), sp_pass_writen(), sp_execute_opbuf(), sp_execute_opbuf_noflush(), sp_check_opbuf_usage(), sp_do_read_n(). - Use those return values to propagate errors instead of exiting. In some places this has to wait for core API changes (error handling for chip_readb, chip_readn, chip_write) hence comments are added instead. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add additional error handling to pcidev_readbar() callers.stefanct2013-08-2312-2/+36
| | | | | | | | | | | This is mostly a leftover of Niklas' "remove exit call from pcidev_init" patch. While not explicitly necessary detecting errors early is usually a good idea. Signed-off-by: Niklas Söderlund <niso@kth.se> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce serialport_config().stefanct2013-08-232-46/+60
| | | | | | | | | | This allows to easily reconfigure a serial port as needed in the Bus Pirate speedup patch. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* getrevision.sh: Make sure we don't get translated output.stefanct2013-08-171-8/+10
| | | | | | | | | (And explicitly require bash.) Signed-Off-By: Joerg Mayer <jmayer@loplof.de> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Allow physmap_common() to round address ranges to page boundaries.stefanct2013-08-141-21/+39
| | | | | | | | | | | | | | Automatically round address ranges requested from rphysmap() to page boundaries. Other physmap() variants were not changed so this is safe regarding unmapping. I had also to shorten the readbility defines for the physmap_common parameters to make the calls fit a single line. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Automatically unmap physmap()s.stefanct2013-08-1414-102/+92
| | | | | | | | | | | | Similarly to the previous PCI self-clean up patch this one allows to get rid of a huge number of programmer shutdown functions and makes introducing bugs harder. It adds a new function rphysmap() that takes care of unmapping at shutdown. Callers are changed where it makes sense. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add getrevision.sh utility script.stefanct2013-08-142-1/+229
| | | | | | | | | | | | This allows to retrieve various data from SCM systems (git and svn) and use them in the build process to better indicate which source was used. For now only use it for the upstream (i.e. svn) revision number, which was previously implemented by an awful line in the Makefile. Signed-Off-By: David Hendricks <dhendrix@google.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Increase flashrom release number to 0.9.7.stefanct2013-08-131-1/+1
| | | | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: David Hendricks <dhendrix@google.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 19.stefanct2013-08-135-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASUS P8H77-V LE http://www.flashrom.org/pipermail/flashrom/2013-June/011127.html - HP Pegatron IPMEL-AE (Evans-GL6) Reported by Idwer on IRC - MSI MS-7379 (G31M) http://paste.flashrom.org/view.php?id=1726 - MSI MS-7816 (H87-G43) http://www.flashrom.org/pipermail/flashrom/2013-July/011349.html - MSI MS-9830 (IM-945GSE-A, A9830IMS) http://paste.flashrom.org/view.php?id=1730 - Supermicro X8SAX http://paste.flashrom.org/view.php?id=1717 NOT OK: - Intel D2700MUD http://paste.flashrom.org/view.php?id=1723 - Intel DQ45CB http://www.flashrom.org/pipermail/flashrom/2013-August/011369.html Chipsets: - Add PCI ID for Intel's Coleto Creek. - Mark Intel H87 (0x8c4a) as OK. http://www.flashrom.org/pipermail/flashrom/2013-July/011349.html Miscellaneous: - ichspi: Fix printing address ranges if space is divided by FPB. - Tiny other stuff. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* An unused programmer parameter is a sign that the user wanted to eitherhailfinger2013-08-131-5/+15
| | | | | | | | | | | | | | do something not supported by the programmer or misspelled a parameter which may be essential for the given programmer. Aborting is the only safe choice. If the programmer parameter is unused because of an error during programmer init, aborting would have happened anyway due to that error. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix verification operation.stefanct2013-08-122-6/+7
| | | | | | | | | | | | | | | | | | | I broke this in r1702 where I enabled avoidance of the verification step if we did not modify anything in the erase/write step. The problem is that all_skipped is initialized to true and hence it would only ever verify if there have been changes noted in the erase/write step. This obviously breaks the verification operation (-v/--verify) because there we never enter the erase/write loop. The better alternative would be to enable (the implicit) verification in the write loop and not in cli_classic.c. This would require a bigger change due to the existance of dont_verify_it. Eventually this is the right thing to do but not so shortly before a release. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Detect AMD Yangtze (found in Kabini and Tamesh).stefanct2013-08-083-6/+67
| | | | | | | | | | | | | | | | | | | | | | | The PCI ID of the LPC bridge doesn't change between Hudson-2/3/4 and Yangtze (Kabini/Temash) but the SPI interface does. Bail out in case we detect Yangtze and add infrastructure to distinguish other families too for further refactorings. Also, add ASRock IMB-A180 to the laptop whitelist and refine the IMC warning a bit. Tested on ASRock IMB-A180 with and w/o USE_YANGTZE_HEURISTICS, and by Chris Goodrich from Sage on - SB600 - SB700 - SB800 - Hudson 3 (A70M) - Kabini Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* dediprog: Fix crash if usb_open() fails.stefanct2013-07-301-0/+4
| | | | | | | Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* sbxxx: Handle active IMCs in AMD chipsets.stefanct2013-07-255-21/+235
| | | | | | | | | | | | Detect and temporarily disable the IMC while accessing the flash. Disable writes on default, but allow the user to enforce it. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rename Numonyx and ST (SGS/Thomson) chips to Micron.stefanct2013-07-251-955/+676
| | | | | | | | | | | | | Micron acquired Numonyx and asked us to change the vendor names to "Micron". For the chips clearly emerging from the former manufacturers we (will) use "Micron/Numonyx/ST" and the original name for the rest. Resorting the chip entries makes the diff unreadable, hence the stand-alone commit. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 18.stefanct2013-07-2518-106/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASUS C60M1-I http://www.flashrom.org/pipermail/flashrom/2013-February/010578.html - ASUS P8H77-I http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html - ASUS P8H77-M http://www.flashrom.org/pipermail/flashrom/2013-May/010994.html - ASUS P8P67 LE (B2) http://www.flashrom.org/pipermail/flashrom/2013-May/010972.html - Elitegroup GeForce6100PM-M2 (V3.0) http://www.flashrom.org/pipermail/flashrom/2013-July/011177.html - GIGABYTE GA-P55A-UD7 http://www.flashrom.org/pipermail/flashrom/2013-July/011302.html - MSI B75MA-E33 (MS-7808) http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html - MSI H77MA-G43 (MS-7756) http://www.flashrom.org/pipermail/flashrom/2013-April/010853.html - MSI KA780G (MS-7551) http://paste.flashrom.org/view.php?id=1617 - SAPPHIRE IPC-E350M1 Reported by xvilka on IRC - Supermicro X8DTG-D http://www.flashrom.org/pipermail/flashrom/2013-July/011305.html NOT OK: - ASRock Fatal1ty Z77 Performance http://www.flashrom.org/pipermail/flashrom/2013-January/010467.html - ASRock Z68 Extreme4 http://www.flashrom.org/pipermail/flashrom/2013-May/010984.html - ASUS P8B75-M LE http://www.flashrom.org/pipermail/flashrom/2013-April/010867.html - ASUS P8P67-M PRO http://www.flashrom.org/pipermail/flashrom/2013-February/010541.html - ASUS P8Z68-V LE http://www.flashrom.org/pipermail/flashrom/2013-February/010582.html - Intel DQ77MK http://paste.flashrom.org/view.php?id=1603 - Supermicro X9DRD-7LN4F http://paste.flashrom.org/view.php?id=1582 - Supermicro X9SCE-F http://www.flashrom.org/pipermail/flashrom/2013-February/010588.html - Supermicro X9SCM-F http://www.flashrom.org/pipermail/flashrom/2013-February/010527.html - Tyan S7066 http://www.flashrom.org/pipermail/flashrom/2013-March/010630.html Chipsets: - Marked Intel B75 as tested http://www.flashrom.org/pipermail/flashrom/2013-March/010659.html - Marked Intel H77 as tested http://www.flashrom.org/pipermail/flashrom/2013-March/010607.html - Removed 10de:03e2 because it is apparently the MCP61 host bridge. It was reclassified to Host Bridge in the PCI device ID database and there is at least one report suggesting this configuration too: http://www.flashrom.org/pipermail/flashrom/2012-August/009716.html - Added MCP89 which hopefully works with the code for previous versions. Thanks to James Laird for submitting this change. Tested flash chips: - Atmel AT25DF641(A) to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2013-June/011113.html - Atmel AT25F512 to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2013-April/010904.html Also, change its ID according to Modification of PCN SC040401A: "There has been a change in the returned value of the Product Identification (RDID) command, the AT25F512A RDID code is 65h compared to 60h from the AT25F512 product." It seems to be quite likely that all AT25F512 are fully functional relabeled AT25F1024 chips. There are even some hints in the datasheet: in table 6 they stress that address pin 16 needs to be low under all circum- stances; while continuous reads can wrap around on the AT25F1024 the DS notes "For the AT25F512, the read command must be terminated when the highest address (00FFFF) is reached." OTOH the lock bit semantics are different, but this has not been tested thoroughly - Atmel AT25F512A to PREW (+PREW) http://paste.flashrom.org/view.php?id=1569 - Eon EN25F05 to PREW (+PREW) http://paste.flashrom.org/view.php?id=1571 - Macronix MX25L12805(D) to PREW (+REW) http://www.flashrom.org/pipermail/flashrom/2013-April/010913.html - Spansion S25FL256S......0 and S25FL512S to P/!R!E!W (+P) Tested by Stefan Tauner - Micron/Numonyx/ST M25PX80 to PREW (+PREW) Tested by Stefan Tauner - Micron/Numonyx/ST N25Q032..3E and N25Q128..3E to PREW (+PREW) Tested by Stefan Tauner - Micron/Numonyx/ST N25Q256..3E and N25Q512..3G to P/!R!E!W (+P) Tested by Stefan Tauner - SST SST25VF040B to PREW (+PREW) http://paste.flashrom.org/view.php?id=1574 - SST SST25VF040B.REMS to PREW (+EW) http://paste.flashrom.org/view.php?id=1575 - ST M25P05-A to PREW (+PREW) http://paste.flashrom.org/view.php?id=1576 - ST M29W512B to PREW (+W) http://www.flashrom.org/pipermail/flashrom/2013-March/010635.html - Winbond W25Q64.W to PREW (+PREW) Tested by the chromiumos guys. - Winbond W25Q128.V to PREW (+REW) http://www.flashrom.org/pipermail/flashrom/2013-June/011108.html - Winbond W25X20 to PREW (+PREW) http://www.flashrom.org/pipermail/flashrom/2013-May/010990.html Miscellaneous: - Add Lenovo X201 to the laptop whitelist. - Add chip IDs for the ESMT F25L..QA family. - Add chip IDs for a few Macronix MX25 models. - The list of flashchips is not sorted strictly alphabetically and should not be either. Refine the comment explaining the scheme on top of the list. - Support -L output of chip sizes with up to 6 decimal places (up to 4 Gb). - Use z length modifier in (more) prints for size_t types. - Remove chips >16MB again because our current implementation of memory mapping the flash chip violates common rules by mapping a window as large as the chip. This leads to failing mmaps as can be seen here: http://paste.flashrom.org/view.php?id=1695 - Document spispeed parameter of linux_spi (and fix some leaks). - Rephrase the "multiple chips detected" message because it was confusing. - Skip verification step if the image is equal to the flash contents. - Tiny other stuff. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Most parts are also Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* uintptr_t-ify map_flash_region functions.stefanct2013-07-176-30/+28
| | | | | | | | | | | | | | | | | | | unsigned long is not the right type for manipulating pointer values. Since C99 there are suitable unsigned and signed types available, namely uintptr_t and intptr_t respectively. Use them in functions assigned to programmers' map_flash_region fields and their callers where applicable. This patch also changes the display width of all associated address values in physmap.c to 16/8 hex characters depending on the actual size by introducing a macro PRIxPTR_WIDTH and exploiting printf's * field width specifier. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* print.c: Fix multiline support.stefanct2013-07-171-13/+38
| | | | | | | | | | | | - Use the reentrant tokenizer version strtok_r to break up vendor and model names in print.c. - Add implementation of strtok_r for mingw (strtok_r is POSIX only). - Free allocated temporary memory again. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Differentiate ultimate error messages depending on programmer used.stefanct2013-07-151-18/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With every newly supported programmer the information regarding reboots on failures becomes more ridiculous. With this patch it is only shown when the internal programmer module was selected. Example outputs for external programmers: 1) non-fatal: […] Reading current flash chip contents... done. FAILED at 0x00000000! Expected=0xff, Found=0x28, failed byte count from 0x00000000-0x0001ffff: 0x1fde7 ERASE FAILED! FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. Please check the connections (especially those to write protection pins) between the programmer and the flash chip. If you think the error is caused by flashrom please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom@flashrom.org, thanks! 2) fatal: […] Verifying flash... FAILED at 0x00000000! Expected=0x0f, Found=0xff, failed byte count from 0x00000000-0x0001ffff: 0x1fde6 Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom@flashrom.org, thanks! Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: David Hendricks <dhendrix@google.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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