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* Add ich_descriptor_tool to decode all flash descriptors stored in a flash ↵stefanct2011-12-246-2/+1135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | dump file This patch adds an external utility that shares most of the existing descriptor decoding source code. Additionally to what is available via FDOC/FDOD this allows to access: - the softstraps which are used to configure the chipset by flash content without the need for BIOS routines. on ICH8 it is possible to read those with FDOC/FDOC too, but this was removed in later chipsets. - the ME VSCC (Vendor Specific Component Capabilities) table. simply put, this is an SPI chip database used to figure out the flash's capabilities. - the MAC address stored in the GbE image. Intel thinks this information should be confidential for ICH9 and up, but references some tidbits in their public documentation. This patch includes the human-readable information for ICH8, Ibex Peak (5 series) and Cougar Point (6 series); the latter two were obtained from leaked "SPI Flash Programming Guides" found by google. Data regarding ICH9 and 10 is unknown to us yet. It can probably found in: "Intel® ICH7, ICH8, ICH9 and ICH10 — SPI Family Flash Programming Guide" Information regarding the upcoming Panther Point chipset is also not included. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Matthias Wenzel <bios@mazzoo.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix programmer-centric probe (patch v2)mkarcher2011-12-221-2/+3
| | | | | | | | | | | | | | | As reported by Stefan Tauner on IRC, the new programmer-centric logic is broken by re-using occupied members of the flashes array when changing to the next programmer. This fixes it. patch v2: prevent probing one chip per programmer even if the array is full. Using a do-while loop was a bad idea. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ft2232_spi: fix arm-usb-ocd and arm-usb-ocd-hhailfinger2011-12-201-0/+4
| | | | | | | | | | | | | These devices have an additional output buffer which is activated only by pulling ADBUS4 low. This patch was real-life tested with arm-usb-ocd; arm-usb-ocd-h should be the same (as it shares the same documentation). Signed-off-by: Paul Fertser <fercerpav@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Speed up dediprog SPI page writeshailfinger2011-12-201-6/+170
| | | | | | | | | | | | | | | All chips which use spi_chip_write_256 should be written at native speed. Chips using spi_chip_write_1 or spi_chip_write_aai will still be slow. Thanks to Steven A. Falco for testing with a ST/Numonyx M25P16. Thanks to David Hendricks for testing with a Winbond W25Q64. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Steven A. Falco <sfalco@coincident.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Cross-compilation fixeshailfinger2011-12-202-25/+100
| | | | | | | | | | | | | | | | | | | | | | | Switch from host OS detection to target OS detection. Complain about unknown target OS/architecture. Disable annoying format string warnings on DJGPP. Native and cross-compilation now usually just require setting CC. Examples: make CC=i586-pc-msdosdjgpp-gcc make CC="clang -m64" make CC=i686-w64-mingw32-gcc Tested for a boatload of native and cross compilation configurations. There is a new target "make libpayload" in case you don't want to specify all tools by hand. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Have all programmer init functions register bus masters/programmershailfinger2011-12-2014-251/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | All programmer types (Parallel, SPI, Opaque) now register themselves into a generic programmer list and probing is now programmer-centric instead of chip-centric. Registering multiple SPI/... masters at the same time is now possible without any problems. Handling multiple flash chips is still unchanged, but now we have the infrastructure to deal with "dual BIOS" and "one flash behind southbridge and one flash behind EC" sanely. A nice side effect is that this patch kills quite a few global variables and improves the situation for libflashrom. Hint for developers: struct {spi,par,opaque}_programmer now have a void *data pointer to store any additional programmer-specific data, e.g. hardware configuration info. Note: flashrom -f -c FOO -r forced_read.bin does not work anymore. We have to find an architecturally clean way to solve this. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add struct flashctx * parameter to all functions accessing flash chips.hailfinger2011-12-1842-541/+727
| | | | | | | | | | | | | | | | | All programmer access function prototypes except init have been made static and moved to the respective file. A few internal functions in flash chip drivers had chipaddr parameters which are no longer needed. The lines touched by flashctx changes have been adjusted to 80 columns except in header files. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use struct flashctx instead of struct flashchip for flash chip accesshailfinger2011-12-1429-269/+301
| | | | | | | | | | | | | | | | | | | | | | | struct flashchip is used only for the flashchips array and for operations which do not access hardware, e.g. printing a list of supported flash chips. struct flashctx (flash context) contains all data available in struct flashchip, but it also contains runtime information like mapping addresses. struct flashctx is expected to grow additional members over time, a prime candidate being programmer info. struct flashctx contains all of struct flashchip with identical member layout, but struct flashctx has additional members at the end. The separation between struct flashchip/flashctx shrinks the memory requirement of the big flashchips array and allows future extension of flashctx without having to worry about bloat. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Update URLs in print.chailfinger2011-12-081-72/+72
| | | | | | | | | | | Move Asus A8Jm, Asus M6Ne to the laptop section. No working URL for the A8Jm found. Signed-off-by: Benjamin Bellec <b.bellec@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1472 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 9stefanct2011-12-022-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ABIT NF-M2S http://www.flashrom.org/pipermail/flashrom/2011-October/008155.html - ASUS P5K-VM http://www.flashrom.org/pipermail/flashrom/2011-October/008172.html - ASUS M5A99X EVO http://www.flashrom.org/pipermail/flashrom/2011-October/008152.html - ASUS Z8PE-D12 http://www.flashrom.org/pipermail/flashrom/2011-November/008195.html - PC Engines Alix.2d3 http://www.flashrom.org/pipermail/flashrom/2011-November/008244.html NOT OK: - ASUS P8H61 PRO http://www.flashrom.org/pipermail/flashrom/2011-November/008308.html - ASUS P8P67 (rev. 3.1) http://www.flashrom.org/pipermail/flashrom/2011-November/008292.html - MSI MS-7613 (Iona-GL8E) http://www.flashrom.org/pipermail/flashrom/2011-November/008295.html - MSI MS-7635 (H55M-ED55) http://www.flashrom.org/pipermail/flashrom/2011-October/008167.html - Supermicro X9SCL http://www.flashrom.org/pipermail/flashrom/2011-November/008254.html - ZOTAC H67-ITX WiFi http://paste.flashrom.org/view.php?id=902 Tested flash chips: - mark Pm29F002T as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-October/008171.html - mark AMIC A49LF040A as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-November/008244.html - mark Winbond W39V040FC as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-November/008281.html - source format fixes Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unsignify lengths and addresses in chip functions and structsstefanct2011-11-2322-143/+150
| | | | | | | | | | Push those changes forward where needed to prevent new sign conversion warnings where possible. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1470 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for ASUS A7N8X-VM/400stefanct2011-11-192-0/+11
| | | | | | | | | http://www.flashrom.org/pipermail/flashrom/2011-November/008274.html Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for ASRock ConRoeXFire-eSATA2stefanct2011-11-162-0/+2
| | | | | | | | | | | | | | The reverse engineering was done by Joshua. The actual patch was fabricated by Paul with some polishing by Stefan. Success log: http://www.flashrom.org/pipermail/flashrom/2011-November/008257.html Signed-off-by: Joshua Roys <roysjosh at gmail.com> Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for ASUS P4GV-LA (Guppy)stefanct2011-11-152-0/+2
| | | | | | | | | | | | | | | | | The reverse engineering was done by Joshua. The actual patch was fabricated by Stefan. Request: http://www.flashrom.org/pipermail/flashrom/2011-November/008241.html Success report: http://paste.flashrom.org/view.php?id=914 Signed-off-by: Joshua Roys <roysjosh@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Tested-by: Mugendai <mugendai42@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1467 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* board_enable.c: Make it8712f_gpio_set genericstefanct2011-11-142-31/+81
| | | | | | | | | | | | | | | This looks suspiciously like intel_ich_gpio_set. Based on that, add board enables for the ASUS P5N-D and P5N-E SLI. This was tested by Guillaume Poirier-Morency on a P5N-D: http://www.flashrom.org/pipermail/flashrom/2011-August/007706.html Signed-off-by: Joshua Roys <roysjosh@gmail.com> Small changes were also contributed and Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Create a directory for documentation filesstefanct2011-11-132-0/+18
| | | | | | | | | | Move the serprog specification there and document a few things we could not figure out on intel platforms yet. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: fix ich_init_opcodes() calls in ich_init_spi()stefanct2011-11-131-2/+2
| | | | | | | | | | | | | | By calling it early ichspi_lock was not set up correctly in accordance with the corresponding register, hence ich_init_opcodes() was always trying to programming the opcodes instead of reading them in from the opmenu in case of a locked down configuration. Thanks to Jonathan A. Kollasch for reporting this bug. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Register Parallel/LPC/FWH programmers the same way SPI programmers are ↵hailfinger2011-11-0922-252/+293
| | | | | | | | | | | | | | | | | | | | | registered. All programmers are now calling programmer registration functions and direct manipulations of buses_supported are not needed/possible anymore. Note: Programmers without parallel/LPC/FWH chip support should not call register_par_programmer(). Additional fixes: Set max_rom_decode.parallel for drkaiser. Remove abuse of programmer_map_flash_region in it85spi. Annotate several FIXMEs in it85spi. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-By: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: print flash descriptor dependent information only when it is validstefanct2011-11-081-26/+33
| | | | | | | | | Also, fix some coding style issues. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: add support for Intel Hardware Sequencingstefanct2011-11-083-15/+319
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the new opaque programmer framework this patch adds support for Intel Hardware Sequencing on ICH8 and its successors. By default (or when setting the ich_spi_mode option to auto) the module tries to use swseq and only activates hwseq if need be: - if important opcodes are inaccessible due to lockdown - if more than one flash chip is attached. The other options (swseq, hwseq) select the respective mode (if possible). A general description of Hardware Sequencing can be found in this blog entry: http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/ Besides adding hwseq this patch also introduces these unrelated changes: - Fix enable_flash_ich_dc_spi to pass ERROR_FATAL from ich_init_spi. The whole error handling looks a bit odd to me, so this patch does change very little. Also, it does not touch the tunnelcreek method, which should be refactored anyway. - Add null-pointer guards to find_opcode and find_preop to matches the other opcode methods better: curopcodes == NULL has some meaning and is actively used/checked in other functions. TODO: adding real documentation when we have a directory for it Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: use a variable to distinguish ich generations instead of ↵stefanct2011-11-064-81/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi_programmer->type The type member is enough most of the time to derive the wanted information, but - not always (e.g. ich_set_bbar), - only available after registration, which we want to delay till the end of init, and - we really want to distinguish between chipset version-grained attributes which are not reflected by the registered programmer. Hence this patch introduces a new static variable which is set up early by the init functions and allows us to get rid of all "switch (spi_programmer->type)" in ichspi.c. We reuse the enum introduced for descriptor mode for the type of the new variable. Previously magic numbers were passed by chipset_enable wrappers. Now they use the enumeration items too. To get this working the enum definition had to be moved to programmer.h. Another noteworthy detail: previously we have checked for a valid programmer/ich generation all over the place. I have removed those checks and added one single check in the init method. Calling any function of a programmer without executing the init method first, is undefined behavior. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add opaque programmer registration infrastructurehailfinger2011-11-048-5/+150
| | | | | | | | | | | | | An opaque programmer does not allow direct flash access and only offers abstract probe/read/erase/write methods. Due to that, opaque programmers need their own infrastructure and registration framework. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for Sun Ultra 40 M2stefanct2011-11-022-0/+34
| | | | | | | | | | | | Failure report with logs: http://www.flashrom.org/pipermail/flashrom/2011-October/008158.html Success report: http://paste.flashrom.org/view.php?id=889 Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix all ASUS P5GD* board enablesstefanct2011-10-222-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes related to P5GD1 variants: - Reorder "P5GD1 Pro" in print.c and include a DMI patter to its board enable - Add an untested "P5GD1(-VM)" board enable and add an entry to print.c - Add P5GD1-VM/S variant as reported by "Limer" Changes related to P5GD(2/C) variants: - Fix the name of "P5GDC-V Deluxe" board enable and add a DMI pattern and print.c entry. NB: there is no "P5GDC-V" board. - Add a generic match for P5GD(2/C)* boards with a not tested tag. This are the potential targets for this according to the asus ftp: ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/ Unsupported variants of the P5GD2: P5GD2, P5GD2 Deluxe, P5GD2 Pro, P5GD2-X (P5GD2 Premium is already tested) (there seems to be also a P5GD2-TVM/GB/SI in the wild, which is not known to asus :) Unsupported variants of the P5GDC: P5GDC Pro, P5GDC-MX (P5GDC Deluxe and P5GDC-V Deluxe are already tested) References: P5GD1 PRO (dmi "P5GD1 PRO") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, *0x814e* http://www.coreboot.org/pipermail/flashrom/2010-August/004539.html P5GD1 (dmi "P5GD1") The non-pro version seems to match the pro pci pattern, but could be distinguished by the SATA ID of 1043:2604 vs. 1043:2601: https://launchpadlibrarian.net/62167576/Lspci.txt or a DMI pattern of course. P5GD1-VM (dmi "P5GD1-VM") This does also match the current PCI IDs. https://bugs.launchpad.net/ubuntu/+source/linux/+bug/465379 - P5GD2 Premium (dmi "P5GD2-Premium") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d http://www.flashrom.org/pipermail/flashrom/2010-August/004555.html - P5GDC-V Deluxe (dmi "P5GDC-V") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d http://www.flashrom.org/pipermail/flashrom/2010-September/004939.html - P5GDC Deluxe (dmi "P5GDC") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d http://www.flashrom.org/pipermail/flashrom/2010-September/004684.html - P5GDC Pro, P5GDC-MX, P5GD2-X, P5GD2 Pro, P5GD2 no useful logs found - P5GD2-Deluxe (dmi "P5GD2-Deluxe") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d https://bugs.launchpad.net/ubuntu/+source/foomatic-filters/+bug/572514 - P5GD2-TVM/GB/SI (dmi "P5GD2-TVM/GB/SI") smbus: 0x8086, 0x266a, 0x1043, 0x266a; audio: 0x8086, 0x2668, 0x1043, *0x81a7* https://bugs.launchpad.net/ubuntu/+source/linux/+bug/462500 Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> and due to the tremendous interest... ;) Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* serprog: small improvementsstefanct2011-10-223-37/+39
| | | | | | | | | | | - rename serprog_delay parameter to usecs - fix code style, (output) formatting issues and comments - sp_docommand: remove unnecessary malloc+memcpy and fix formatting Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for ABIT AV8stefanct2011-10-212-0/+18
| | | | | | | | | | | | | | | | I disassembled the write enable and the write disable functions from the Award BIOS image and reconstructed C code to understand for myself what happens. For details see: http://www.flashrom.org/pipermail/flashrom/2011-October/008033.html I compared the download pages of both, abit AV8 and abit AV8-3rd Eye, and the BIOS downloads are the same. So it's save to assume that this board enable works on both versions. Tested on AV8. Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 8stefanct2011-10-216-23/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASUS Crosshair II Formula http://www.flashrom.org/pipermail/flashrom/2011-September/007888.html - ASUS K8N http://paste.flashrom.org/view.php?id=856 - ASUS M2N-E SLI http://www.flashrom.org/pipermail/flashrom/2011-September/007909.html - ASUS M3N78-VM http://www.flashrom.org/pipermail/flashrom/2011-May/006496.html - ASUS M4A78LT-M LE http://www.flashrom.org/pipermail/flashrom/2011-September/007869.html - ASUS M4A89GTD PRO http://www.flashrom.org/pipermail/flashrom/2011-February/005824.html - MSI A75MA-G55 (MS-7696) http://www.flashrom.org/pipermail/flashrom/2011-October/008055.html - PCCHIPS M598LMR (V9.0) http://www.flashrom.org/pipermail/flashrom/2011-October/008051.html - ECS P4VXMS (V1.0A) http://www.flashrom.org/pipermail/flashrom/2011-September/007986.html - Foxconn P4M800P7MA-RS2 http://www.flashrom.org/pipermail/flashrom/2011-October/008114.html - GIGABYTE GA-P67A-UD3P http://www.flashrom.org/pipermail/flashrom/2011-September/007930.html - GIGABYTE Z68MX-UD2H-B http://www.flashrom.org/pipermail/flashrom/2011-October/008080.html - ZOTAC Fusion-ITX WiFi (FUSION350-A-E) http://www.flashrom.org/pipermail/flashrom/2011-October/008011.html NOT OK: - ASUS P8B-E/4L http://www.flashrom.org/pipermail/flashrom/2011-October/008047.html - ASUS P8B WS http://www.flashrom.org/pipermail/flashrom/2011-October/008081.html Tested chipsets: - MCP78S (:075d) http://www.flashrom.org/pipermail/flashrom/2011-August/007612.html - VT8233 (:3074) http://www.flashrom.org/pipermail/flashrom/2011-September/007986.html - SiS 530 (:0530) http://www.flashrom.org/pipermail/flashrom/2011-October/008051.html - P67 (:1c46) http://www.flashrom.org/pipermail/flashrom/2011-September/007930.html - Z68 (:1c44) http://www.flashrom.org/pipermail/flashrom/2011-October/008080.html Tested flash chips: - mark AMIC A29002T as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-October/008085.html - mark Eon EN29F002(A)(N)T as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-October/008053.html - mark EonEN25F16 as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-February/005824.html - mark Macronix MX29F002(N)T as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-October/008083.html - mark Pm39LV040 as TEST_OK_PR http://www.flashrom.org/pipermail/flashrom/2011-September/007942.html - mark Pm39LV010 as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-September/007942.html - mark SST49LF008A as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-September/007989.html - mark SyncMOS {F,S,V}29C51002T as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-October/008052.html - mark W39V040B as write tested http://www.flashrom.org/pipermail/flashrom/2011-October/008114.html - mark W39V040C as TEST_OK_PREW http://www.flashrom.org/pipermail/flashrom/2011-October/008114.html - remove superfluous line break in enable_flash_ich_dc_spi - m->M in "min" and "max" (voltage) in print_wiki.c - spi25: get rid of unneccessary line breaks (on failed probes) which is Acked-by: Uwe Hermann <uwe@hermann-uwe.de> - rayer_spi.c: Remove double word: `s/the the/the/` which is Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> The parts added until 2011-10-14 (most of this patch) were Acked-by: Uwe Hermann <uwe@hermann-uwe.de> everything else is Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the GOEPEL PicoTAP programmer.uwe2011-10-203-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://www.goepel.com/en/jtagboundary-scan/hardware/picotap.html This device is actually a JTAG adapter, but since it uses standard FT2232 A interface pins, it can be easily used as SPI programmer (tested it here successfully). PicoTAP supports only 5V output, so one needs to reduce this to 3.3V in a same manner as DLP Design DLP-USB1232H, see http://flashrom.org/FT2232SPI_Programmer#DLP_Design_DLP-USB1232H for details. The PicoTAP pin-out is as follows: PicoTAP | SPI ---------+------- TCK | SCLK TMS | CS# TDI | SO TDO | SI /TRST | - GND | GND +5V | VCC, HOLD# & WP# after 3.3V regulator I managed to run PicoTAP in 10MHz, 15MHz and 30MHz modes (by forcing DIVIDE_BY), against SST25VF016B SPI flash, read/write/erase all worked fine (write seems somewhat slow). Signed-off-by: Samir Ibradžić <sibradzic@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: add (partially) dead support code for Intel Hardware Sequencingstefanct2011-10-203-13/+113
| | | | | | | | | | This was done to ease the review. Another patch will hook up (and explain) this code later. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* TIAO/DIYGADGET USB Multi-Protocol Adapter (TUMPA) support.uwe2011-10-143-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Thanks to TIAO/DIYGADGET for sponsoring a test device! This is an FTDI FT2232H based device which provides an easily accessible JTAG, SPI, I2C, serial breakout. The SPI part can be used to flash SPI flash chips using flashrom. http://www.diygadget.com/tiao-usb-multi-protocol-adapter-jtag-spi-i2c-serial.html http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User%27s_Manual#SPI_Connector_1 There are two SPI connectors (pin headers) on the board: SPI1, which is connected to the FT2232H's A interface, and SPI2, which is connected to the chip's B interface. Both can be used to flash SPI chips: flashrom -p ft2232_spi:type=tumpa,port=A flashrom -p ft2232_spi:type=tumpa,port=B The default interface is A, so for SPI1 you can also just write: flashrom -p ft2232_spi:type=tumpa I tested all operations on both interfaces, everything works fine. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Revert "Unsignify lengths and addresses in chip functions and structs"stefanct2011-09-1814-58/+58
| | | | | | | | | | | | | | | | | | | | - probe_timing was changed to unsigned although we use negative values for special cases - some code was not changed along hence did no longer compile: * dediprog's read and write functions * linux_spi's read and write functions - it introduced a number of new sign conversion warnings (http://paste.flashrom.org/view.php?id=832) To be safe this patch reverts all changes made in r1448, a corrected patch will follow later. Thanks to idwer for pointing out the problem first! Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1450 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: inform the user about the consequences of the security override strapstefanct2011-09-181-0/+6
| | | | | | | | | | | | | | Ibex Peak SPI Programming Guide: The PCH has a mechanism to set up to 5 address ranges from HOST access. These are defined in PR0, PR1, PR2, PR3 and PR4 in the PCH EDS. These address ranges are NOT unlocked by assertion of Flash descriptor Override. Also, the datasheets mention the bit in their description of FRAP but not PR[N]. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1449 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unsignify lengths and addresses in chip functions and structsstefanct2011-09-1814-58/+58
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: unlock PR register restrictions on ICH8+ if not locked downstefanct2011-09-171-0/+27
| | | | | | | | | | | Tested-by: Shailendra Sodhi (predecessor/proof of concept patch) http://www.flashrom.org/pipermail/flashrom/2011-August/007717.html Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: add prettyprinting for PR registers on ICH8+stefanct2011-09-171-14/+30
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: don't touch the nonexistent(?) BBAR register on ICH8stefanct2011-09-171-14/+12
| | | | | | | | | | | | | There is no sign of BBAR (BIOS Base Address Configuration Register) in the public datasheet (or specification update) of the ICH8. Also, the offset of that register has changed between ICH7 (SPIBAR + 50h) and ICH9 (SPIBAR + A0h), so we have no clue if or where it is on ICH8. Better don't try to touch it at all and assume/hope it is 0. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: improve prettyprint_opcodesstefanct2011-09-171-12/+23
| | | | | | | | | add headers for the columns and some decoding into human readable format. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDODstefanct2011-09-154-12/+597
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptor sections that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content section: describes the image and some generic properties (number of sections, offset of sections, PCH/ICH and MCH/PROC strap offsets and lengths) - component section: identify the different SPI flash chips and their capabilities. - region section similarly to a partition table this describes the different regions. the content of FLREG* is derived from this section. - master section defines SPI master (host, ME, GbE) access rights of the individual regions. the content of PR* is derived from this section. this is only a part of the data included in the descriptor. other information can be retrieved from a complete binary dump of the descriptor region only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of all supported flash chips (together with their RDIDs) are stored in the same format in table in a descriptor section (which is used by the ME apparently). a later patch will use the macros outside of ichspi.c which is the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h (else they would be moved in the follow-up patch). because this patch relies on (compiler) implementation-specific layouting of bit-fields, it checks for correct layout before taking any action on runtime. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* serprog: add SPI supportstefanct2011-09-153-73/+206
| | | | | | | | | | | | Adds a new opcode (0x13) that just relays SPI bytes and wires it up to be usable within serprog.c. Checks for mandatory opcodes are moved around and changed a bit, but non-SPI programmers should not be harmed by this patch. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add printing of chip voltage ranges to print_wiki.cstefanct2011-09-141-14/+31
| | | | | | | | | | | - add voltage ranges - center some headers (test values OK, No, ? are centered via wiki templates) - fix style error in header (align:right -> text-align:right) Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make the laptop warning less scary if unsurestefanct2011-09-131-6/+8
| | | | | | | | | | | | Telling the user to use "force_I_want_a_brick" if it is not even a laptop, is a bit over-the-top. Introduce a new laptop parameter "this_is_not_a_laptop" that allows to force operation, but only if the detection is not sure. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add probe/read support for the Catalyst CAT28F512 chip.uwe2011-09-132-0/+25
| | | | | | | | | | | | | Write and erase are NOT yet supported! Probe and read are tested by Andrew Morgan and Uwe Hermann on Intel NICs. Signed-off-by: Andrew Morgan <ziltro@ziltro.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Reformat -L output and add printing of chip voltage ranges to print.cstefanct2011-09-121-58/+217
| | | | | | | | | | | | | | | | | | | | besides adding output for the voltage ranges, this patch also changes various aspects of the -L output: - sizes are right aligned now with a fixed length of 5 - space between columns is selectable with a constant - test results are always shown in the same column ("PR" and " R" instead of "PR" and "R ") - vendor and device names are split on a delimiter (currently '/') and spread over mutliple lines but only if the tokens are not too short. all other columns are printed on the first line of a chip. - voltage ranges are printed in verbose mode only it also gets rid of POS_PRINT and digits Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Xilinx parallel III (DLC5) programing cablehailfinger2011-09-122-21/+76
| | | | | | | | | | | | The rayer_spi driver defaults to the RayeR cable, but selecting other predefined pin layouts with the type= parameter is possible: flashrom -p rayer_spi:type=xilinx Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Print out the flash chip found after the probing loop in verbose modestefanct2011-09-111-0/+7
| | | | | | | | | | | | | This allows easier identification of the flash chip used in verbose logs. There is no (additional) output if * -c is used to specify a flash chip, or * multiple chips are detected, or * no chips are detected. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Revamp the warning of failing to set BIOS write enable in enable_flash_ichstefanct2011-09-091-7/+8
| | | | | | | | | | | - introduce a new variable 'wanted' that is used instead of 'new' - use 'new' for the actual value contained in BIOS_CNTL after we tried to write it - rephrase the warning which now also includes the old and new values besides the wanted one Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add initial Atmel AT49LH002 FWH/LPC chip support.uwe2011-09-082-0/+37
| | | | | | | | | | | | | | The chip code is untested, only one erase function out of two is currently implemented, and unlocking/printlocking is not yet supported. Thanks Mattias Mattsson <vitplister@gmail.com> for the initial patch! Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Change programmer selection in cli and generic codehailfinger2011-09-084-87/+103
| | | | | | | | | | | | | | | Bugfix: Do not accept multiple conflicting --programmer selections. Restriction: Do not accept multiple --programmer selections even if there is no conflict. Unexport the programmer variable. programmer_init requires the programmer as first parameter. The default programmer selection is now part of cli_classic. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Small fixes for the linux_spi programmer code.uwe2011-09-071-7/+12
| | | | | | | | | Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Mark the GIGABYTE GA-8I945GZME-RH and SST SST25LF040A as supported.uwe2011-09-072-1/+2
| | | | | | | | | | | | | | | Success report: http://www.flashrom.org/pipermail/flashrom/2011-June/006797.html lspci and other info: http://www.flashrom.org/pipermail/flashrom/2010-August/004531.html Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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