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* more NetBSD fixes (w/ patch)mkarcher2010-02-162-2/+3
| | | | | | | | | | | | | Cast input to tolower() to unsigned char to work around how tolower() is implemented on NetBSD. Also, use CPPFLAGS (rather than overriding CFLAGS) for the NetBSD/DragonFly build example. Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@905 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Some programmers want to run certain functions during programmerhailfinger2010-02-142-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | shutdown, but the function choice depends on the code path taken during programmer init. Rather than rebuilding the whole init logic in the shutdown function, it is now possible to register functions for execution on programmer shutdown. The behaviour is similar to atexit(), but the registered functions will be run on programmer shutdown instead of on exit and the functions will be called with a void * argument that is specified on registration. Registered functions must have the prototype void function(void *); and will be executed in reverse registration order directly before calling the programmer-specific shutdown() function. It is recommended to have shutdown() only disable programmer/hardware access and leave all code path sensitive shutdown to functions registered with register_shutdown(). The most prominent use case is resetting the EC after flashing on laptops. Note: There are quite a few code paths in flashrom which proceed to terminate flashrom without any programmer shutdown. Those code paths will not get the benefit of register_shutdown() and they should be changed wherever possible. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use uname -p instead of -m on NetBSD so we get the righthailfinger2010-02-141-1/+1
| | | | | | | | | | architecture library name. Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add SPI mode diagnostics for all post-MCP55 (nForce 5) chipsets fromhailfinger2010-02-131-1/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nvidia. Huge thanks to Michael Karcher for reverse engineering the MCP67 chipset and writing a spec. Due to this, we were able to use the chinese wall technique for 100% clean room reverse engineering. This patch doesn't touch any of the new registers, it only reads them. Assuming that read has no side effects, this patch is a no-op and safe. We need "flashrom -V" output from all post-MCP55 (nForce 5) chipset boards. Please indicate if your board uses SPI flash or LPC flash (if you know it). Note: That output is only helpful if it is created with patched flashrom and if is from the first run of flashrom after a cold boot (reset or Ctrl-Alt-Del is not sufficient). There is a pattern based on which we can probably detect which flash type is present on the board. Thanks to Alessandro Polverini for testing earlier iterations of this patch. Note: The MCP67 should work. I guessed that the other recent Nvidia chipsets would work in a similar way, and created a simplified do-nothing catchall chipset enable function which dumps some info and instructs the user to send more info. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Kill an erroneous .erase introduced in r900.hailfinger2010-02-131-1/+0
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Adds support for the Intel E28F004S5 flash chip.snelson2010-02-132-0/+26
| | | | | | | | | Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* SPI RES is the most unreliable way to identify chips because it onlyhailfinger2010-02-121-4/+17
| | | | | | | | | | | | | | | | | | returns a 1-byte ID for most chips. For every given ID out there, probably a dozen incompatible flash chips match it. We already refuse to identify a chip with RES if that chip responds to RDID (3 bytes, good match), and with this patch we additionally refuse RES if the chip responds to REMS (2 bytes, still a good match). This increases matching accuracy a lot. Besides that, the RDID/REMS response checking has been cleaned up for better readability. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Linking in support for the internal programmer doesn't make sense if youhailfinger2010-02-124-67/+85
| | | | | | | | | | | | | | | only need hardware (ioport, memory) access. Split internal.c into internal.c and hwaccess.c. Note: This patch was created by "svn cp internal.c hwaccess.c" and then removing stuff from both files. That's why you can't apply the patch as-is before running the svn cp. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix erase blocks for Winbond W25X{10,20,40,80} SPI chips. The Winbond W25X10 ↵snelson2010-02-121-24/+0
| | | | | | | | | | | and related chips only have 4k and 64k blocks and only accept erase commands: 20h, d8h, and c7h. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix DMI match logicmkarcher2010-02-121-1/+2
| | | | | | | | | This bug slipped in on changing back match-specific to match-any Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@896 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* At long last, the day has come, and we can bury full-chip erase once andhailfinger2010-02-113-224/+6
| | | | | | | | | | | | | | | | for all. Back in November 2008(!) I proposed the first version of the flexible sector-based erase structure, and now we can finally rip out the old full-chip erase code without ill effects. Rejoice and party! Thanks to everyone who made this possible, especially to Sean Nelson who converted the majority of flash chips to sector erase. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This megapatch rewrites substantial parts of ICH SPI to actually do whathailfinger2010-02-111-53/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the SPI layer wants instead of its own weird idea about commands (running unrequested commands, running modified commands). Besides that, there is a fair share of cleanups as well. - Add JEDEC_EWSR (Enable Write Status Register) to default commands. - Mark a no longer used opcode/preopcode table as unused. - Declare all commands as non-atomic/standalone by default. The ICH SPI driver has no business executing commands (preopcodes) automatically if they were not requested. - Automatically adjust preopcode/opcode pairings (like WREN+ERASE) based on what the SPI layer requested. The ICH SPI driver has no business executing altered opcode pairs as it sees fit. - Fix incomplete initialization in the case of a locked down chipset. Leaving the first 4 opcodes with uninitialized pairings had unpredictable results. - switch() exists for a reason. Nested if() checking on the same variable is an interesting style. - Actually check if the requested readcnt/writecnt for a command is supported by the hardware instead of delivering corrupt/incomplete commands and data. - If a command has unsupported readlen/writelen, complain loudly to the user. - Use find_opcode instead of open-coding the same stuff in a dozen variations. - Introduce infrastructure for updating the command set of unlocked chipsets on the fly. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Document the rules for DMI matching with PCI subsystem IDs.hailfinger2010-02-041-3/+9
| | | | | | | | | | | The rules may change in the future, but right now it is important that the comments match the code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@893 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Allow DMI supported board enables with subsystem ID zero.mkarcher2010-02-041-1/+2
| | | | | | | | | This is needed for the Intel SE440BX-2 as well as the Asus P5A. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Properly initialize USB device in dediprog driver.oxygene2010-02-041-0/+2
| | | | | | | | | | | That's necessary to use bulk transfers, and just the right thing in any case. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a second set of PCI IDs for the Tekram P6Pro-A5 (trivial).uwe2010-02-041-1/+1
| | | | | | | | | | | (Re-)tested on hardware, detection works OK. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Create a physical memory mapping function which requests cached readonlyhailfinger2010-02-023-7/+65
| | | | | | | | | | | | | | | | | | | | | | | | memory. This should take care of picky Linux kernels which do not allow uncached mappings to cached areas. Handle mapping failure gracefully (no forced exit()) if the caller specifies it. Such cached areas which can handle mapping failure are DMI tables and coreboot tables. On failure we just ignore those tables. That is not perfect, but a lot better than aborting flashrom due to an error in nonessential functionality. This should fix flashrom on a sizable number of machines where it currently aborts early. Yes, I could have exploited a Linux kernel bug to "solve" this, but relying on such bugs is not exactly the best idea. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Vincent Pelletier <plr.vincent@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Adds support for ST M29W512B. Tested and works for me.snelson2010-02-012-0/+25
| | | | | | | | | Signed-off-by: Jeffrey A. Kent <jakent@gmail.com> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add the Tekram P6Pro-A5 board as supported (trivial).uwe2010-01-312-0/+2
| | | | | | | | | | | | | | | The board doesn't need a board-enable, writing works out of the box. Also, the board can only decode 256KB. I verified this by writing a 512KB image of random bytes (which fails), whereas 256KB of random bytes can be written correctly. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Complete the addition of Feature Bits for all Jedec based chips.snelson2010-01-284-195/+316
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add FEATURE_SHORT_RESET, FEATURE_LONG_RESET, and FEATURE_EITHER_RESET rewrite jedec functions to use getaddrmask convert write_49f002 to write_jedec_1 convert write_w39v040c to write_jedec_1 convert probe_w39v040c to probe_jedec convert write_49lf040 to write_jedec_1 convert write_pm29f002 to write_jedec convert write_29f040b to write_jedec_1 convert probe_29f040b to probe_jedec convert erase_chip_29f040b to erase_chip_block_jedec convert erase_sector_29f040b to erase_sector_jedec convert write_m29f002b to write_jedec convert write_m29f002t to write_jedec convert *_29f002 to *_jedec decouple unused files from Makefile: am29f040b.c en29f002a.c m29f002.c mx29f002.c pm29f002.c sst49lf040.c w39v040c.c w49f002u.c Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Anders Juel Jensen <andersjjensen@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* The GIGABYTE GA-7ZM has a maximum decode size (parallel chips) of 512 KB.uwe2010-01-281-7/+11
| | | | | | | | | | | | | | | | | | | Add this information to the new field in the board-enable table. We match the board via two sets of PCI IDs. However, as we don't need a board-enable function for this board (it works out of the box; well, at least if you remove the JP9 jumper on the board), change the code to allow NULL as value for the board-enable function. There will likely be more boards in the future where we want to record a maximum decode size but which don't need a board-enable. This is hardware-tested on the GIGABYTE GA-7ZM by successfully writing a 512KB image of random bytes to a chip in this board. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@885 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Avoid bogus gcc warningmkarcher2010-01-271-2/+2
| | | | | | | | | | | | recent gcc/glibc combinations warn about ignoring the fgets() result. The problem exists on Ubuntu 9.10 with current updates. This "fix" of the non-problem (as I check ferror() afterwards) should even be a (negligible) performance optimization. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Andrew Morgan <ziltro@ziltro.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@884 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Windows wants UNC names for COM ports >9 (legacy COM ports only work with ↵oxygene2010-01-261-1/+9
| | | | | | | | | | | | | | | one digit). As UNC also works for smaller names, just retarget all requests for dev=COMx on win32 to \\.\COMx. Tested with large and small COM port numbers on XP. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Open binary files in binary mode. No change on UNIX (or Mac OS,oxygene2010-01-251-2/+2
| | | | | | | | | | according to its documentation), but fixes operation on Windows. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the SST39SF512 chip.uwe2010-01-232-0/+27
| | | | | | | | | | | All operations tested by me, works fine. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* backout unintentional chunk.stepan2010-01-221-1/+1
| | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add write support.hailfinger2010-01-222-11/+18
| | | | | | | | | | | | Speed up reads by a factor of 4 by switching block size from 4 to 16. Add support for 4 byte RDID. Add USB error decoding via usb_strerror. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch fixes the use of CFLAGS and CPPFLAGS in the flashrom makefilestepan2010-01-211-8/+8
| | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert the following chips to block_erasers: snelson2010-01-205-48/+405
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SST28SF040A SST29EE010 SST29LE010 SST29EE020A SST29LE020 SST39SF010A SST39SF020A SST39SF040 SST39VF512 SST39VF010 SST39VF020 SST39VF040 SST39VF080 SST49LF002A/B SST49LF003A/B SST49LF004C SST49LF008A SST49LF008C SST49LF016C SST49LF020 SST49LF020A SST49LF040 SST49LF040B SST49LF080A SST49LF160C Extend sst28sf040 to include chip and sector functions for block_eraser. Extend sst49lfxxxc to include chip, sector, block erasers functions for block_erasers. Extend sst_fwhub to include chip and sector functions for block_erasers. Add copyrights to changed files. Killed erase_sst_fwhub. Killed erase_49lfxxxc. NULL A/A mux mode full chip erasers. Ignore block locks in erase/write. Change comments from "PP mode" to "A/A mux mode" Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Boards: Remove it8705_rom_write_enable.libv2010-01-201-50/+30
| | | | | | | | | Should be functionally the same as it8705f_write_enable_2e. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Boards: Add max_rom_decode_parallel entry to board enable table.libv2010-01-202-67/+64
| | | | | | | | | This is a quick fix for board specific parallel addressing limits. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Matching board via DMImkarcher2010-01-205-57/+253
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a board is not uniquely identifiable by PCI device/subsystem IDs, a string can be specified to be looked for (case-sensitive, substring or anchored) for now in one of the following DMI items in addition to matching the PCI IDs: - System Manufacturer - System Product Name - System Version - Baseboard Manufacturer - Baseboard Product Name - Baseboard Version Strings are anchored re-like (^ at the beginning, $ at the end), but there are no plans to support full regular expressions and matched to any of the mentioned fields. The match is only made if DMI info is available and the string matches. If no DMI info is available and the PCI IDs match, a warning is printed as the board can not be autodetected. It's still open to discussion whether we add an DMI override switch to specify a string that will definitely match, and whether this switch is only used if no DMI is available or whether it overrides or augments DMI data. DMI data is currently read using dmidecode. This tool is available for all major platforms except MacOS X. I heard that there also is a MacOS X version of dmidecode, but didn't investigate that. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Luc Verhaegen <libv@skynet.be> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix SyncMOS S29C51004T, which has 512 uniform 1k sectors.snelson2010-01-191-1/+1
| | | | | | | | | Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert ST to block erasers:snelson2010-01-191-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ST M25P05-A ST M25P05.RES ST M25P10-A ST M25P10.RES ST M25P20 ST M25P40 ST M25P40-old ST M25P80 ST M25P16 ST M25P32 ST M25P64 ST M25P128 ST M29F002B ST M29F002T/NT ST M29F040B ST M29F400BT ST M29W010B ST M29W040B ST M50FLW040A ST M50FLW040B ST M50FLW080A ST M50FLW080B ST M50FW002 ST M50FW016 ST M50FW040 ST M50FW080 ST M50LPW116 Add erase_chip_stm50flw0x0x to stm50flw0x0x.c Add copyright to stm50flw0x0x.c Fix block sizes and counts Omit M50FLW0x0x mixed sector/block eraser Convert the used 82802ab functions to their stm50flw0x0x equivalents Fix incorrect sizes as found by Carl-Daniel. Add back M50FLW0x0x mixed sector/block eraser sans function pointer. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert chips to block_erasers:snelson2010-01-193-49/+452
| | | | | | | | | | | | | | | | | | SyncMOS S29C31004T SyncMOS S29C51001T SyncMOS S29C51002T SyncMOS S29C51004T TI TMS29F002RT TI TMS29F002RB SyncMOS chips have Uniform sector; boot blocks on chips are made up of uniform sectors but have locking. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Dediprog SF100 support.hailfinger2010-01-195-1/+441
| | | | | | | | | | | | | | | | | | | | | | | | Reverse engineered from USB logs. I never touched that programmer nor did I ever see the associated software. Disabled by default until it is complete. The driver needs to be hooked up to the SPI core before it will do anything besides init and diagnostics. I successfully reverse engineered all commands, but some are still somewhat magic. Logs from "flashrom -p dediprog -V" are appreciated. Probe and read should work, erase/write is expected to explode. The programmer will set voltage to 0 on exit. Thanks a lot to Stefan Reinauer and Patrick Georgi for providing USB logs and for testing the result. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add eraseblock functions to self-check. It doesn't make sense to havehailfinger2010-01-191-9/+28
| | | | | | | | | | | | different layouts for the same function on one chip. Keep going if an error is found, we want all errors to be reported in one fell swoop. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Converted chips to block_erasers:snelson2010-01-191-35/+314
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | W_25X10 W_25X20 W_25X40 W_25X80 W_25X16 W_25X32 W_25X64 W_29C011 W_29C020C W_29C040P W_29EE011 W_39V040A W_39V040B W_39V040C W_39V040FA W_39V080A W_49F002U W_49V002A W_49V002FA W_39V080FA W_39V080FA_DM Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert chips to block_erasers:snelson2010-01-194-21/+283
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ST_M25PE10 ST_M25PE20 ST_M25PE40 ST_M25PE80 ST_M25PE16 PMC_25LV010 PMC_25LV016B PMC_25LV020 PMC_25LV040 PMC_25LV080B PMC_25LV512 PMC_39F010 PMC_49FL002 PMC_49FL004 SANYO_LE25FW203A SPANSION_S25FL016A Added spi_block_erase_d7 for PMC chips. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add Intel NM10 chipset enable.hailfinger2010-01-191-0/+1
| | | | | | | | | | | | | | Public chipset documentation available at http://www.intel.com/Assets/PDF/datasheet/322896.pdf Tested on NM10-based customer reference board from Intel. Signed-off-by: David Hendricks <dhendrix@google.com> Acked-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix A25L40PU and A2540PT due to incorrect full-chip block size is incorrect.snelson2010-01-181-2/+2
| | | | | | | | | | Thanks to hailfinger's self-check-erase routine for catching this. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Flashrom performs a self-check on every startup before it even starts tohailfinger2010-01-181-20/+61
| | | | | | | | | | | | | | initialize any programmer. That way, compiler errors and code errors will be caught before they can do any harm. This patch adds an eraseblock structure self-check. It also modifies the self-check code to consistently run all checks even if one check failed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* The write and erase column in the --list-supported-wiki output werehailfinger2010-01-181-1/+1
| | | | | | | | | | swapped. Thanks to Michael Karcher for noticing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support for Spansion S25FL008Amkarcher2010-01-122-0/+27
| | | | | | | | | | Tested with read/erase/write (including verify). I only wrote the image that was read before - don't want to brick my laptop. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Don't use "byte" as identifier.mkarcher2010-01-123-14/+14
| | | | | | | | | | Some mingw declares a global identifier "byte", causing -Werror -Wshadow to break compilation. This patch renames all identifiers called "byte". Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Enable -Wshadow, clean code for thatmkarcher2010-01-125-13/+11
| | | | | | | | | | | | | | This is not just for fun. We hit a real bug on BSD with the outl macros. The macro variable tmp collided with the tmp from outer scope. second revision, now also taking care of inb/inw/inl. While that shadowing did not introduce bugs (yet), of course it breaks the build on BSD when -Wshadow is enabled. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Luc Verhaegen <libv@skynet.be> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Chipset: Fix sis5x0 register write verification.libv2010-01-101-13/+3
| | | | | | | | | | | Also remove separate sis 5596 routine: superio code will be handled separately, which then turns this routine into the sis 5511 chipset enable. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* If neither internal (old default) nor dummy (safe default) programmerhailfinger2010-01-101-2/+31
| | | | | | | | | | | | | | | are selected, we must pick a sensible default programmer. Since there is no reason to prefer a particular external programmer, we abort compilation if more than one of them is selected. If only one is selected, it is clear that the user wants that one to become the default. This fixes single-programmer compilation. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert all messages in sb600spi.c to the new message infrastructure.hailfinger2010-01-101-30/+19
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Change a few probe timings to TIMING_FIXME. They previously hadhailfinger2010-01-101-5/+5
| | | | | | | | | | | TIMING_IGNORED, but now they use probe_jedec directly or indirectly and that function does not ignore probe timing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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