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* serprog: add SPI supportstefanct2011-09-153-73/+206
| | | | | | | | | | | | Adds a new opcode (0x13) that just relays SPI bytes and wires it up to be usable within serprog.c. Checks for mandatory opcodes are moved around and changed a bit, but non-SPI programmers should not be harmed by this patch. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add printing of chip voltage ranges to print_wiki.cstefanct2011-09-141-14/+31
| | | | | | | | | | | - add voltage ranges - center some headers (test values OK, No, ? are centered via wiki templates) - fix style error in header (align:right -> text-align:right) Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make the laptop warning less scary if unsurestefanct2011-09-131-6/+8
| | | | | | | | | | | | Telling the user to use "force_I_want_a_brick" if it is not even a laptop, is a bit over-the-top. Introduce a new laptop parameter "this_is_not_a_laptop" that allows to force operation, but only if the detection is not sure. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add probe/read support for the Catalyst CAT28F512 chip.uwe2011-09-132-0/+25
| | | | | | | | | | | | | Write and erase are NOT yet supported! Probe and read are tested by Andrew Morgan and Uwe Hermann on Intel NICs. Signed-off-by: Andrew Morgan <ziltro@ziltro.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Reformat -L output and add printing of chip voltage ranges to print.cstefanct2011-09-121-58/+217
| | | | | | | | | | | | | | | | | | | | besides adding output for the voltage ranges, this patch also changes various aspects of the -L output: - sizes are right aligned now with a fixed length of 5 - space between columns is selectable with a constant - test results are always shown in the same column ("PR" and " R" instead of "PR" and "R ") - vendor and device names are split on a delimiter (currently '/') and spread over mutliple lines but only if the tokens are not too short. all other columns are printed on the first line of a chip. - voltage ranges are printed in verbose mode only it also gets rid of POS_PRINT and digits Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Xilinx parallel III (DLC5) programing cablehailfinger2011-09-122-21/+76
| | | | | | | | | | | | The rayer_spi driver defaults to the RayeR cable, but selecting other predefined pin layouts with the type= parameter is possible: flashrom -p rayer_spi:type=xilinx Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Print out the flash chip found after the probing loop in verbose modestefanct2011-09-111-0/+7
| | | | | | | | | | | | | This allows easier identification of the flash chip used in verbose logs. There is no (additional) output if * -c is used to specify a flash chip, or * multiple chips are detected, or * no chips are detected. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Revamp the warning of failing to set BIOS write enable in enable_flash_ichstefanct2011-09-091-7/+8
| | | | | | | | | | | - introduce a new variable 'wanted' that is used instead of 'new' - use 'new' for the actual value contained in BIOS_CNTL after we tried to write it - rephrase the warning which now also includes the old and new values besides the wanted one Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add initial Atmel AT49LH002 FWH/LPC chip support.uwe2011-09-082-0/+37
| | | | | | | | | | | | | | The chip code is untested, only one erase function out of two is currently implemented, and unlocking/printlocking is not yet supported. Thanks Mattias Mattsson <vitplister@gmail.com> for the initial patch! Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Change programmer selection in cli and generic codehailfinger2011-09-084-87/+103
| | | | | | | | | | | | | | | Bugfix: Do not accept multiple conflicting --programmer selections. Restriction: Do not accept multiple --programmer selections even if there is no conflict. Unexport the programmer variable. programmer_init requires the programmer as first parameter. The default programmer selection is now part of cli_classic. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Small fixes for the linux_spi programmer code.uwe2011-09-071-7/+12
| | | | | | | | | Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Mark the GIGABYTE GA-8I945GZME-RH and SST SST25LF040A as supported.uwe2011-09-072-1/+2
| | | | | | | | | | | | | | | Success report: http://www.flashrom.org/pipermail/flashrom/2011-June/006797.html lspci and other info: http://www.flashrom.org/pipermail/flashrom/2010-August/004531.html Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add Intel Tunnel Creek chipset support, mark it as tested.uwe2011-09-071-1/+45
| | | | | | | | | | | | | | | | | | | | | | Intel's Tunnel Creek chipset supports both an SPI and an LPC bus. Set the chipset table entry for Tunnel Creek to the new function enable_flash_tunnelcreek(), which will read the hardware straps and return support for the bus that has been used for booting. This function uses ich_init_spi() with ich_generation set to 7 for initializing the SPI bus if necessary. SPI functionality tested on actual hardware, Tunnel Creek LPC interface not tested yet (missing hardware for that). Log file / success report: http://www.flashrom.org/pipermail/flashrom/2011-September/007823.html Signed-off-by: Ingo Feldschmid <ifel@msc-ge.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Kill all exit() calls in chipset_enable.c.uwe2011-09-061-5/+4
| | | | | | | | | Signed-off-by: Tadas Slotkus <devtadas@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix linux_spi.c build on 32bit systems.uwe2011-09-061-2/+2
| | | | | | | | | Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Linux SPI subsystem (spidev).uwe2011-09-034-0/+180
| | | | | | | | | | | | | | | | | | | | | | | | See http://www.kernel.org/doc/Documentation/spi/spidev for an introduction. Usage is as follows: flashrom -p linux_spi:dev=/dev/spidevX.Y where X is the bus number, and Y device. It accepts an optional parameter 'speed' which allows to set the SPI clock speed in kHz. Tested on an Atmel AVR32AP7000 board (NGW100 Network Gateway Kit), see below, which was used to program a ThinkPad X60, but it should work on every other Linux system, too. http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4102) Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce ERROR_FATAL, abort upon failed chipset enables.uwe2011-09-033-2/+10
| | | | | | | | | Signed-off-by: Tadas Slotkus <devtadas@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 7stefanct2011-09-038-28/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add Asus Crosshair IV Extreme to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-August/007640.html - add Biostar N68S3+ to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-September/007788.html - add P7H55-M LX to the list of supported boards although flashrom works correctly, it is marked as not ok, because flashing the vendor image will break the LAN interface. - add GA-X58A-UD7 to the list of supported boards http://paste.flashrom.org/view.php?id=739 - add Asus P4P800-VM to print.c (has a working board enable) - add Asus K8V-X to print.c reported by florz http://paste.flashrom.org/view.php?id=742 - add Intel D865GLC to print.c as non-working (ICH5 with BIOS lock enable) reported by jmd on IRC http://paste.flashrom.org/view.php?id=775 - add Intel DH67CF to print.c as non-working (H67 with BIOS lock enable and locked ME region) http://www.flashrom.org/pipermail/flashrom/2011-September/007789.html - add ECS P4M800PRO-M (V1.0A) to the list of supported boards reported by dweg on IRC (hot flashed a SST49LF040B, original was W39V040B) - add X8DTU-6TF+ to print.c (needs ME unlocking) http://www.flashrom.org/pipermail/flashrom/2011-August/007553.html - add Shuttle FH67 (used in the SH67H3 barebone) to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-August/007749.html - add Tyan S2912 to the list of supported boards reported by erlan on IRC - add ZOTAC GeForce 8200 to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-August/007612.html - mark AT25DF321A as TEST_OK_PROBE http://www.flashrom.org/pipermail/flashrom/2011-August/007553.html - mark 28F001BN/BX-T as TEST_OK_PR http://www.flashrom.org/pipermail/flashrom/2011-July/007208.html - rename MX29F002 http://patchwork.coreboot.org/patch/2794/ - mark SST39SF040 as fully tested reported by Florian 'florz' Zumbiehl http://paste.flashrom.org/view.php?id=742 - mark SST49LF040B as fully tested reported by dweg on IRC and later by Armin on the ml: http://www.flashrom.org/pipermail/flashrom/2011-August/007764.html - mark H55 chipset as OK http://www.flashrom.org/pipermail/flashrom/2011-July/007432.html - mark H67 chipset as OK http://www.flashrom.org/pipermail/flashrom/2011-August/007749.html - mark a MCP61 version as OK http://www.flashrom.org/pipermail/flashrom/2011-September/007788.html - add preliminary X79 (patsburg) PCI IDs 0x1d40 was reported already as working (not archived in our pipermail?) http://marc.info/?l=flashrom&m=130683026218257&w=2 - mark "82557/8/9/0/1 Ethernet Pro 100" in nicintel.c as working http://www.flashrom.org/pipermail/flashrom/2011-August/007480.html - rename some chips that had gratuitous "probing" suffixes: - SST25VF010.REMS - SST25VF040.REMS - M25P05.RES - M25P10.RES some other chip names with suffixes are needed due to lack of support for multiple probe functions per chip. this is explained here: http://www.flashrom.org/pipermail/flashrom/2011-August/007597.html - remove unneeded nicintel_spi-related function declarations in programmer.h - typos and whitespace fixes - fix Asus P4P800-E Deluxe detection The original board enable was added before DMI matching and used the IDs of a Promise controller as secondary PCI ID set. The controller could be disabled in the BIOS which would make the board not match. This patch uses the SMBus controller instead and adds a DMI pattern. This was Tested-by: Michael Schneider <vdrportal_midas at gmx dot de> - add "Sealed-case PC" to the list of chassis type (as indicating "not a laptop") This is Acked-by: Idwer Vollering <vidwer@gmail.com> the fix for the typo unusued -> unused is Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier@gmail.com> everything else is Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> And everything was reviewed and Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Shorten some board enable related function nameshailfinger2011-08-315-21/+20
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix printing of the Boot BIOS Straps on Intel chipsetsstefanct2011-08-271-48/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The meaning of the bits involved has changed several times in the past. This patch takes these changes into account and hence fixes the output of the pretty printing of GCS on all SPI-supported Intel chipsets that are not ICH7 or NM10 (the latter were unaffected, because the defaults were correct). This patch also allows to differentiate Ibex Peak and Cougar Point chipsets from the earlier chipset series (ICH10) by adding new wrapper functions that set "ich_generation" to 11 and 12 respectively. This should not change behavior outside of enable_flash_ich_dc_spi, because the code path for ich_generation >=9 is equal. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> --- defining all those arrays is not very elegant, but i think it is at least very readable this way. improvements are welcome! reviewers should have an eye on the codepaths for ich_generation >= 9. i did not spot a problem, but it should be checked again. alternatively we could just remove the pretty printing of GCS and just output the bits involved. i would like to keep the pch differentiation anyway though, because i feel it will become handy in the future. tested on my QS57-based thinkpad (probe + partial read) git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add AMD Hudson chipset-enable.uwe2011-08-262-2/+6
| | | | | | | | | | | | AMD Hudson has different vendor/device IDs than AMD SBx00, handle that properly. Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Mark the AMD Am29LV008BB chip as fully tested.uwe2011-08-251-1/+1
| | | | | | | | | | | | Thanks Mattias Mattsson <vitplister@gmail.com> for the report. http://www.flashrom.org/pipermail/flashrom/2011-July/007423.html Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Sharp LH28F008BJT-BTLZ1 chip.uwe2011-08-253-0/+86
| | | | | | | | | | | | Tested by Mattias Mattsson <vitplister@gmail.com> on a PowerPC box. Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for ASUS P5LP-LEstefanct2011-08-252-0/+8
| | | | | | | | | | | | | | | | | | Based on the REing of Michael Karcher and a good guess of Idwer Vollering. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Tested-by: Leon Zhang <leoncamel at gmail.com> http://www.coreboot.org/pipermail/flashrom/2010-August/004500.html Tested-by: medhi <nefkongo@hotmail.com> http://paste.flashrom.org/view.php?id=779 Acked-by: Idwer Vollering <vidwer@gmail.com> --- i have added the DMI match and changed the board enable and wiki comments a bit. i am not sure if this is the right way to add it, because there are so many variations, but we can change that later too. git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1419 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Makefile: Fix MinGW build, improve output with bogus CC.uwe2011-08-201-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | As per IRC discussion, the "ARCH :=" line should be moved after any lines which set CC, as it uses CC itself. This fixes the MinGW build. Also, add a "2>/dev/null" in the "ARCH :=" as per suggestion from Stefan Tauner to improve the output in the case CC is bogus: Before: $ make CC=foo /bin/sh: foo: not found Checking for a C compiler... not found. make: *** [compiler] Error 1 After: $ make CC=foo Checking for a C compiler... not found. make: *** [compiler] Error 1 Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move the main() function from flashrom.c to cli_classic.c.uwe2011-08-203-9/+1
| | | | | | | | | | | | | | | | | The file flashrom.c is part of libflashrom and should thus not contain a main() function, that would break compilation of all frontends using libflashrom. Also, cli_classic.c is the right place anyway, as it's the main() of the CLI tool. Rename the simple wrapper cli_classic() in cli_classic.c to main(), as it's not really needed. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Makefile: fix and simplify test program compilationsstefanct2011-08-181-33/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this was totally broken due to the make's shell function's temporal behavior. quote from the gnu make documentation (http://www.gnu.org/s/hello/manual/make/Shell-Function.html): "The commands run by calls to the shell function are run when the function calls are expanded" we have used the shell function to echo the test programs to a file. the file name used was equal for all tests and was overwritten for each test. the result was that all tests (in a single target?) used the last test program because the echoing of the test programs was done before all test compilations(!) see my mail for details: http://lists.gnu.org/archive/html/bug-make/2011-08/msg00010.html also the branching for testing ifeq ($(CONFIG_FT2232_SPI), yes) was unnecessarily complicated. in my approach here i am using verbatim variables (allows to define even complex test programs in the makefile without jumping through hoops) that get exported to environment variables (via "export", reference afterwards with "$$<varname>"). i have also added the missing redirection of stderr to the compiler test and changed the definition of ARCH to use simple expansion (:=). the latter is still wrong, because it uses $(CC) before we check if a compiler is installed... makes the compiler check pretty much useless. The simple expansion just reduces the number of errors printed to 1. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the SST25LF080A flash chipstefanct2011-08-171-30/+60
| | | | | | | | | | | | | Based on the definition of SST25LF040A and the public datasheet available here: http://www.sst.com/dotAsset/40316.pdf Also, move the SST25LF040A up to keep the list ordered alphabetically (while removing the ".RES" suffix). Signed-off-by: Zeus Castro <thezeusjuice@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove unneeded inclusions of chipdrivers.hstefanct2011-08-1613-12/+2
| | | | | | | | | | | | | | | | | | | | | | this is related to the spi split patch as discussed in: http://www.flashrom.org/pipermail/flashrom/2010-February/thread.html#2364 the old commit (r914) log notes: "Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c" there still remain a few cases where chipdrivers.h is needed: dediprog.c (spi_read_chunked and spi_write_chunked) it87spi.c (due to spi_write_enable and spi_read_status_register) wbsio_spi.c (spi_programmer registration only) besides that, there are also non-spi files that do not need it. also, add flash.h to chipdrivers.h because it uses some types of it and remove flashchips.h from print.c Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fixup of r1397:hailfinger2011-08-1511-40/+59
| | | | | | | | | | | | | | | - Mixing uninitialized and initialized local variables leads to confusion. - ft2232_spi error cases should have gotten some error handling, and that's the reason the curly braces were there. - Fixing typos/wording in some places would have been nice given that those places were touched anyway. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ft2232_spi: add support for the Dangerous Prototypes Bus Blasterstefanct2011-08-122-4/+10
| | | | | | | | | | | | | | | | Add support for the Dangerous Prototypes Bus Blaster (v1/v2). The new model is called "busblaster". So far only v2 has been tested, but since both v1 and v2 emulate a Amontec JTAGKEY in the default configuration, it is assumed that v1 should work fine as well. Information about the Busblaster can be found at: http://dangerousprototypes.com/docs/Bus_Blaster Signed-off-by: Steve Markgraf <steve@steve-m.de> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for ASUS P5GD2 Premiumstefanct2011-08-112-1/+4
| | | | | | | | | | | | | | | | | | | | | | This is based on Joshua's patch, but with a DMI pattern, contrary to http://www.flashrom.org/pipermail/flashrom/2010-September/004745.html Rationale: although it looks like all P5GD2/C* might use the same board enable (intel_ich_gpio21_raise), we need to add the variants individually as long as we don't have enough reports to make a better guess. This also guarantees correct output of flashrom -L and -z and on activation of the board enable - not like this: http://www.flashrom.org/pipermail/flashrom/attachments/20100930/2286e5d1/attachment-0003.txt Success report: http://www.flashrom.org/pipermail/flashrom/2010-August/004555.html Also, fix last commit by adding a missing comma. Tested-by: Roberto Malinverni Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add (untested) board enable for Asus P5LD2stefanct2011-08-112-0/+3
| | | | | | | | | | | | | | | | | | There are numerous other variants of the P5LD2 which vary wildly not only in PCB layout but also in northbridges used, number of PCI, PCI-E and DIMM slots etc. This one is for the plain P5LD2 without any suffixes. This patch is essentially a rebased version of Joshua's patch, which was never tested (user did not reply). I have added additional PCI IDs and the DMI pattern and also changed the status to NT. An entry in the print.c table was also added. http://www.flashrom.org/pipermail/flashrom/2010-October/005080.html Signed-off-by: Joshua Roys <roysjosh@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi.c: refactor filling and reading the fdata/spid registersstefanct2011-08-091-78/+57
| | | | | | | | | | | | - add ich_fill_data to fill the chipset registers from an array - add ich_read_data to copy the data from the chipset register into an array - replace the existing code with calls to those functions - minor cosmetic changes Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a board enable for ASUS A8M2N-LA (HP OEM "NodusM3-GL8E")stefanct2011-08-073-1/+4
| | | | | | | | | | | It is based on Joshua Roys' RE. http://www.flashrom.org/pipermail/flashrom/2011-August/007504.html Tested-by: Márton Miklós Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix the A8N-SLI Deluxe board enablestefanct2011-08-062-2/+2
| | | | | | | | | | | | | | | | | | | | | | Long story short: - the A8N in print.c should be A8N-SLI Deluxe as documented - the A8N-SLI Deluxe board enable needs a DMI pattern, else it will get executed on the A8N-SLI Premium unnecessarily. http://www.flashrom.org/pipermail/flashrom/2010-August/004310.html the DMI string is taken from an ubuntu bug report (a real dmidecode or flashrom output was not found). https://bugs.launchpad.net/ubuntu/+source/linux/+bug/807980 - the other A8N-SLI variants seem to work without the board enable A8N-SLI Premium: http://www.flashrom.org/pipermail/flashrom/2010-August/004310.html A8N-SLI: http://www.coreboot.org/pipermail/coreboot/2009-June/049107.html http://www.coreboot.org/pipermail/coreboot/2009-May/049002.html Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix the EP-8NPA7I (for the last time hopefully)stefanct2011-08-062-4/+5
| | | | | | | | | | | | | | | | - retag it as OK (tested by Jonathan Kollasch when he wrote it) http://patchwork.coreboot.org/patch/2106/ - add a line with identical pci ids but a different dmi pattern, so that EP-9NPA7I is also matched. combining multiple boards in one line is problematic due to print.c's detection of board enables - so dont bother for now. http://www.flashrom.org/pipermail/flashrom/2011-June/006878.html See previous commit for additional information. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Clear byte 0x92 of the LPC bridge for all CK804 (and MCP51) chipsetsstefanct2011-08-061-0/+6
| | | | | | | | | | | | | | | | | | | | | | | The OEM BIOS on the EPoX EP-8PA7I and a number of other boards clear byte 0x92 in the LPC bridge configuration space. Do the same for all CK804 chips, assuming this to be some sort of chipset-generic write-enable. Currently the same chipset enable is used for MCP51 (nForce 430). There have been reports of successful writes with its variations (e.g. A8N-LA (Nagami-GL8E)), but they were not tagged as OK. Due to the new "unsupported chipset"-message we will get success reports in the case this patch does not break anything on the MCP51-based boards. See also: http://www.flashrom.org/pipermail/flashrom/2011-July/007252.html http://patchwork.coreboot.org/patch/3176/ Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Acked-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce msg_*dbg2stefanct2011-08-043-3/+10
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rephrase warnings in chipset_enable.cstefanct2011-08-041-22/+22
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Switch to AAI for some more SST chipsstefanct2011-08-011-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Enable AAI for: SST25VF016B SST25VF040B{,.REMS} SST25VF080B Chips that support AAI via a different opcode are annotated with a comment: SST25VF040.REMS SST25LF040A.RES SST25VF080B Tested-by: Joshua Roys <roysjosh@gmail.com> Write time (w/erase) went from 46 s to 21 s. SST25VF016B Tested-by: Noé Rubinstein <nrubinstein@avencall.com> Write time (w/erase) on a dediprog went from 143 mins to 56 mins. Signed-off-by: Joshua Roys <roysjosh@gmail.com> Rebased and Acked-by: Noé Rubinstein <nrubinstein@avencall.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use __func__ instead of __FUNCTION__ as we do elsewhere.uwe2011-07-291-14/+12
| | | | | | | | | | | | | | The __func__ variant is standardized in C99 and recommended to be used instead of __FUNCTION__ in the gcc info page. See also r711 where we did the same change. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make flashrom build on PPC/PowerPC with just "make".uwe2011-07-291-0/+34
| | | | | | | | | | | | Build-tested in a QEMU ppc (Debian) image, and by Andrew Morgan <ziltro@ziltro.com> on real hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Andrew Morgan <ziltro@ziltro.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* extract spi_prettyprint_status_register_amic_a25_srwdstefanct2011-07-291-8/+10
| | | | | | | | | | extract spi_prettyprint_status_register_amic_a25_srwd from spi_prettyprint_status_register_amic_a25l* functions Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* manpage: Document all ft2232_spi and serprog variants.uwe2011-07-281-8/+11
| | | | | | | | | Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Random whitespace and coding-style fixes.uwe2011-07-2820-523/+523
| | | | | | | | | | | | | | Also, indentation fixes, e.g. due to conversion to msg_*, use ARRAY_SIZE where possible, wrap overly long line, etc. Compile-tested. There should be no functional changes. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rename CHIP_BUSTYPE_FOO to BUS_FOO.hailfinger2011-07-2722-348/+348
| | | | | | | | | | It's shorter to type, and we have less problems with the 80 column limit. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Increase flashrom release number to 0.9.4hailfinger2011-07-261-1/+1
| | | | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* add a bunch of new/tested stuff and various small changes 6stefanct2011-07-264-6/+11
| | | | | | | | | | | | | | | | | - add J-7BXAN to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-July/007397.html - fix urls, typos, whitespace etc. - fix counting of supported chips in the wiki output Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> the last one is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> everything else is Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix output of erase_and_write_flash and surroundingsstefanct2011-07-261-13/+16
| | | | | | | | | | | | see http://www.flashrom.org/pipermail/flashrom/2011-July/007220.html for a discussion about the details. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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