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* Allow to easily build all optional modules.stefanct2015-01-191-0/+7
| | | | | | | | | | | | | | | | This patch adds a CONFIG_EVERYTHING flag to the Makefile that sets all CONFIG_* flags to "yes" if they were "no". This provides a comfortable way to ensure maximum code exposure to tools like coverity[0] or clang's scan-build. [0] https://scan.coverity.com/projects/1020 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix support for Macronix MX25L6495F.stefanct2015-01-101-0/+1
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Macronix MX25L6495F.stefanct2015-01-102-0/+38
| | | | | | | | | | This is based on the code sent to the flashrom mailing list by Alex Lu (alexlu6@mxic.com.tw) without sign-off. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refinements for DragonflyBSD.stefanct2015-01-104-15/+11
| | | | | | | | | | | | | - /usr/include/cpu/param.h defines PAGE_MASK already, hence use another name for the respective macro in nicintel_eeprom.c. - Since DragonflyBSD 3.6 DPorts is used as the default package manager. Therefore we should use /usr/local/ instead of /usr/pkg/ on default to fetch libraries. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove defaults for CC and AR.stefanct2015-01-101-2/+0
| | | | | | | | | | | | | AR defaults to "ar" anyway in GNU make and instead of gcc it is probably a better idea to use just cc. The latter allows to build on freebsd 10 without overriding CC or doing symlink tricks (because it uses clang as cc, provides multiple gcc packages but only versioned binaries without any actual "gcc" command name in the path). Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unify target OS and CPU architecture checks.stefanct2015-01-1015-115/+163
| | | | | | | | | | | | | | | | | | | | | | We do CPU architecture checks once for the makefile in arch.h and once for HW access abstraction in hwaccess.c. This patch unifies related files so that they can share the checks to improve maintainability and reduce the chance of inconsistencies. Furthermore, it refines some of the definitions, which - adds "support" for AARCH64 and PPC64, - adds big-endian handling on arm as well as LE handling on PPC64, - fixes compilation of internal.c on AARCH64 and PPC64. Additionally, this patch continues to unify all OS checks in flashrom by adding a new helper macro IS_WINDOWS. The old header file for architecture checking is renamed to platform.h to reflect its broader scope and all new macros are add in there. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Allow to easily set a global path prefix for libraries and include files.stefanct2015-01-102-13/+9
| | | | | | | | | Gets rid of a few DOS-specific Makefile hacks. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1863 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refine revision handling.stefanct2015-01-102-2/+17
| | | | | | | | | | | | | Up to now, when compiling flashrom outside a VCS it would print two warnings that are not very clear to the user. This patch adds a new auxilary function to getrevision.sh and uses it in the makefile to print a single and more meaningful message to the user while hiding the warnings from getrevision.sh. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1862 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix wrong density encoding on Intel Silvermont.stefanct2015-01-052-30/+26
| | | | | | | | | | | | | | Silvermont (Bay Trail, Rangeley, Avoton) seems to still use the old density encoding with 3 bits per chip. Documentation is unavailable (held concealed by Intel) but thanks to the efforts of Tai-Hong (Type) Wu the layout is clear now. This patch is based on his one but solves the issue differently thus reducing the code complexity. Signed-off-by: Tai-Hong Wu <thwu@lunartoday.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the MSTAR I2C ISP protocol.stefanct2014-12-205-0/+339
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Basically, among other chips, MSTAR manufactures SoCs that equip TV sets and computer screens, and it seems that all of their products use the same in-system programming protocol. Basically, they use the DDC channel of VGA or DVI connectors, which is actually an I2C bus, to encapsulate SPI frames (the flash chip is connected to the SoC through an SPI bus). I wrote this patch since the screen I bought had a software bug, and the manufacturer only released a new firmware binary, but no tool or instructions on flashing it. More details can be found here: http://boeglin.org/blog/index.php?entry=Flashing-a-BenQ-Z-series-for-free(dom) I only read code from Linux kernel archives published by Acer to figure out the protocol (for a touchscreen controller and an NFC chip, both by MSTAR, that share the same ISP protocol), so I don't think there are any legal problems with it. Compilation is currently disabled by default in the Makefile. If in doubt, additional Makefile bugs were added by Stefan. Signed-off-by: Alexandre Boeglin <alex@boeglin.org> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix handling of write protection at register space address +2.stefanct2014-12-202-41/+53
| | | | | | | | | | | | | | | Since r1833 we added the offset of the virtual register in several functions, which produced segfaults. This patch renames a few parameters and reorganizes/fixes various parts of the changelock_regspace2_block() function - hence the rather big diff. Thanks to Roman Lebedev for reporting this issue and testing numerous revisions of this patch. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Spansion S25FL127S.stefanct2014-12-123-3/+80
| | | | | | | | | | | | | | | | | | | | | | This flash chip can be configured (one time) to use 64 KiB or 256 KiB sectors. Additionally, in the 64 KiB mode it supports 16 4 KiB sub-sectors that can be (one time) programmed to be on the top or bottom of the device. The sub-sectors can be erased with the 0x20 opcode but because this opcode does not work with the remaining sectors and flashrom can not cope with that the 0x20 opcode is not supported yet. This patch adds two definitions, one for the 64 KiB and 256 KiB configuration respectively. The device also shares the RDID with the various S25FL128 devices so we have to increase the maximum number of successfully probed chips to 8. The 64 KiB mode was tested on real hardware. Signed-off-by: Jernej Škrabec <jernej.skrabec@planet.si> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Eon EN29LV040 and EN29LV040A.stefanct2014-12-072-1/+28
| | | | | | | | | | Both use the same ID and are mostly identical. Tested-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Intel 82599 10 GbE NICs.stefanct2014-12-051-2/+23
| | | | | | | | | | | | | | | | | | | The Intel 82599 series of 10 GbE controllers has a bit-banged SPI interface that's register-compatible with the one in the 1 GbE controllers, except the register addresses are shifted up by 0x10000, cf. Intel document 331520: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82599-10-gbe-controller-datasheet.pdf This patch was tested with a board that has the 0x10fc device and a Micron M25P40 SPI flash chip. The PCI IDs and names for the devices are per Intel document 331521 https://www-ssl.intel.com/content/dam/www/public/us/en/documents/specification-updates/82599-10-gbe-controller-spec-update.pdf and the PCI SIG device ID registry with small refinements. Signed-off-by: Ed Swierk <eswierk@skyportsystems.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add board enable for GIGABYTE GA-8SIMLFS 2.0.stefanct2014-11-302-0/+3
| | | | | | | | | | | This board was used/sold by Fujitsu. The board enabled was tested (sadly with the wrong image, i.e. one of the GA-8SIMLH images directly from GIGABYTE instead of one from Fujitsu). Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* cbtable.c: Do not unnecessarily duplicate strings.stefanct2014-11-011-8/+4
| | | | | | | | | | | | The strdup calls were a leftover that slipped through the cleanup in r1577. Found-by: Valgrind 3.10.0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1854 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move strtok_r implementation verbatim to helpers.c.stefanct2014-11-013-21/+24
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* dmi.c: make sure we call isprint() correctly.stefanct2014-10-191-1/+1
| | | | | | | | | | | ISO C and POSIX require to call ctype functions with values representable by unsigned char. We have used a char as input so far which might be negative and hence get sign-extended. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1852 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make read before write configurable (infrastructure part).stefanct2014-10-193-17/+50
| | | | | | | | | | | | | | - Introduce a variable in doit() that allows to influence read-before-write and its consequences. - Modify build_new_image so that it still works even if the old content is not read before. - Add copy_old_content() to ease the pain for future patches. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Winbond W25Q40.V chips.stefanct2014-09-091-0/+40
| | | | | | | | | Read-tested by Peter Ruesch. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1850 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* dmi.c: Duplicate returned strings because they are meant to be freed.stefanct2014-09-051-3/+3
| | | | | | | | | Without this patch dmi_shutdown calls free() on read-only strings. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce generic shutdown_free() and remove redundant internal_shutdown().stefanct2014-08-313-7/+7
| | | | | | | | | The former will be useful in cases where cleanup equals a simple call to free(). Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refine physical address mapping of flash chips.stefanct2014-08-305-40/+97
| | | | | | | | | | | | | | | | | | - Create distinct functions for mapping and unmapping for flash chips. - Map only when needed: map before probing and unmap immediately after it. Map again when a single chip was probed successfully before taking any actual actions and clean up afterwards. - Map special function chip registers centrally together with flash space instead of within (some) probing methods after successful probes. - Save the used base addresses of the mappings in struct flashctx as well. - Do not try to (un)map the zero-sized chip definitions that are merely hacks. This also fixes the printing of wrong warnings for these chip definitions introduced in r1765. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Macronix MX23L1654, MX23L6454 and MX23L12854 mask ROMs.stefanct2014-08-202-0/+51
| | | | | | | Signed-off-by: Michael Coppola <michael.n.coppola@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Intel Wildcat Point PCH.stefanct2014-08-205-4/+27
| | | | | | | | | | | The Wildcat Point PCH can be paired with Broadwell or Haswell. This patch was essentially backported from ChromiumOS commit 9bd2af8. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton.stefanct2014-08-205-59/+191
| | | | | | | | | | | | | | | | | | | | | | The core of this patch to support Bay Trail originally came from the Chromiumos flashrom repo and was modified by Sage to support the Rangeley/Avoton parts as well. Because that was not complicated enough already Stefan Tauner refactored and refined everything. Bay Trail seems to be the first Atom SoC able to support hwseq. No SPI Programming Guide could be obtained so it is handled similarly to Lynx Point which seems to be its nearest relative. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Marc Jones <marcj303@gmail.com> Tested-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Thomas Reardon <thomas_reardon@hotmail.com> Tested-by: Wen Wang <wen.wang@adiengineering.com> Acked-By: Marc Jones <marcj303@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refine Flash Component descriptor handling.stefanct2014-08-204-65/+204
| | | | | | | | | | | | | | | Possible values as well as encodings have changed in newer chipsets as follows. - Pre-PCH (i.e. ICH) chipsets had a maximum frequency of 33 MHz for all operations - Since Cougar Point the chipsets support dual output fast reads (encoded in bit 30). - Flash component density encoding has changed from 3 to 4 bits with Lynx Point, currently allowing for up to 64 MB chips. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refine handling chips that exceed maximum programmer sizes.stefanct2014-08-153-21/+21
| | | | | | | | | | | | | | | | - Change check_max_decode() to return the number of (common) busses where the flash chip exceeds the supported size of the programmer. - Refine its signature to use a flashctx pointer only. - Move CLI-related bits to cli_classic.c. - Rename check_max_decode() to count_max_decode_exceedings() to better reflect what it (now) really does. - Refine the messages printed by the caller to better integrate with the new setup, and simplify them. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refactor some CLI-relevant parts.stefanct2014-08-088-109/+128
| | | | | | | | | | | | | | | Begin to move functions that clearly belong to the (command line) user interface out of flashrom's core files like flashrom.c. - Refine messages within check_chip_supported(), rename it to print_chip_support_status() and move it to newly created cli_common.c. - Move flashbuses_to_text() to cli_common.c as well. - Move global verbosity variables to cli_output.c. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unify non-shifted and shifted JEDEC access.stefanct2014-08-087-213/+81
| | | | | | | | | | | | | | | | | | Some Parallel bus chips have a 16-bit mode and an 8-bit mode. They use normal JEDEC addresses for 16-bit mode and shifted addresses (by 1 bit) for 8-bit mode. Some programmers can access them in 16-bit mode, but on all flashrom-supported programmers so far, we access them in 8-bit mode. This means we have to shift the addresses but apart from the addresses we can share the code. This patch makes this possible by checking the chip's FEATURE_ADDR_SHIFTED flag in common JEDEC functions and applying the right addresses respectively. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 21.stefanct2014-08-0615-84/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASUS F2A85-M Reported by various corebooters - ASUS M2N-MX SE Plus Reported by Antonio - ASUS P5LD2 Reported by François Revol - Lenovo ThinkPad T530 Reported and partially authored by Edward O'Callaghan - MSI MS-7502 (Medion MD8833) Reported by naq on IRC - Shuttle AB61 Reported by olofolleola4 - ZOTAC IONITX-F-E Reported by Bernardo Kuri Flash chips: - Atmel AT45DB021D to PREW (+PREW) Reported by The Raven - Atmel AT25F4096 to PREW (+PREW) Reported by 공준혁 - GigaDevice GD25Q16(B) to PREW (+PREW) Reported by luxflow@live.com using a GD25Q16BSIG - Catalyst CAT28F512 Mark erase and write as known bad (not implemented) Miscellaneous: - Various spelling corrections by Daniele Forsi. - Added and refined a bunch of chips originally investigated by Carl-Daniel. - Marked the ARM-USB-OCD-H programmer as tested (reported by Ruud Schramp). - Tiny other stuff. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for S25FL128P, S25FL129P and refine it for S25FL128S chips.stefanct2014-08-063-4/+185
| | | | | | | | | | | | | | | | | | | | | | | | Additionally to the existing S25FL128S......0 definition this patch adds S25FL128P......0, S25FL128P......1 and S25FL128S......1, as well as S25FL129P......0 and S25FL129P......1 definitions. S25FL12xP seem to be the predecessor families of S25FL128S. All associated chips can not be distinguished with RDID alone. Besides the new chips, this patch also fixes the name of the previously supported S25FL128S model with uniform 256 kB sectors (S25FL128P......1 not 0) and adds the hybrid sector version (0) as well. Due to the shared IDs the user has to select the right chip manually with the -c parameter. To make this even possible, this patch enlarges the respective array for results to 6. Tested-by: Antonio Ospite <ao2@ao2.it> with a S25FL129P......0. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ichspi: fix missing set_addr on erases and possible crossings of 256 B ↵stefanct2014-08-051-0/+8
| | | | | | | | | | | | | | | | | | boundaries. Apparently the erase function did never set any address before issuing the erase commands. How could this ever work? Also, according to PCH documentation crossing 256 byte boundaries is invalid and may cause wraparound due to the flash chip's pages. Check for this on reads as well as writes. Thanks to Vladimir 'φ-coder/phcoder' Serbinenko for noticing these issues and providing the initial patch. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* linux_spi: properly convert pointers to kernel's u64.stefanct2014-08-051-2/+2
| | | | | | | | | | | | | | | | | | For arm64 with 32-bit userspace, pointers such as 0xff96ebf8 were incorrectly getting converted to u64_t 0xffffffffff96ebf8 in the spi_ioc_transfer struct which was causing ioctl()s to be rejected by the kernel. With this patch we first cast to uintptr_t (to avoid warnings on architectures where char * are not 64b wide) and then to uint64_t which is always big enough and does not produce warnings. This patch is taken from ChromiumOS' Change-Id: I5a15b4ca5d9657c3cb1ddccd42eafd91c852dd26 Signed-off-by: David Riley <davidriley@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for a bunch of 29GL parallel flash chips.stefanct2014-08-034-10/+754
| | | | | | | | | | | | | | | | | | | | | | 29GL chips use a new 3-Byte device ID probing function at addresses 0x01, 0x0E, 0x0F. Flash chip families supported by this method include... - EON EN29GL - Gigadevice GD29GL (if they really exist) - ISSI (PMC) IS29GL - Macronix MX29GL (+MX68GL1G0F) - Spansion S29GL (+S70GL02G) - Winbond W29GL This patch adds respective flash chip definitions for chips up to 16 MB from Eon, ISSI, Macronix and Winbond. Bigger chips as well as those from Gigadevice and Spansion are left out. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Atmel AT49LH004 and AT49LH00B4.stefanct2014-08-032-6/+80
| | | | | | | | | Also, slightly refine the definition of AT49LH002. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refactor unlocking of many chips with locking at register space address +2.stefanct2014-08-039-315/+248
| | | | | | | | | | | This includes PMC Pm49*, SST 49LF00*, ST M50* and Winbond W39* families. The erase and write test status bits of all affected chips have been reset. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add new programmer for SPI EEPROMs attached to Intel 82580 NICs.stefanct2014-07-285-3/+379
| | | | | | | | | | | | | | | | This patch lets you read and write the EEPROM on 82580-based gigabit NIC cards. So far it has been tested on copper NICs only, but other variants employing this controller should work too. It is a nice substitution for the official eeupdate tool. Speed is quite decent: less than 4 seconds for erases or writes of 32 kB. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rename programmer registration functionshailfinger2014-07-1939-197/+194
| | | | | | | | | | | | | register_programmer suggests that we register a programmer. However, that function registers a master for a given bus type, and a programmer may support multiple masters (e.g. SPI, FWH). Rename a few other functions to be more consistent. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for AMD Bolton chipset.stefanct2014-07-151-20/+26
| | | | | | | | | | | | | | SPI controller on the bolton chipset uses the same 3-bit speed settings as Yangtze, but is otherwise the same as the Hudson chips. Note that the Bolton RRG doesn't specify a speed setting for the bit setting of 0b111, so I'm assuming that it's the same setting as Yangtze. Signed-off-by: Martin Roth <martin.roth@se-eng.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refine messages regarding AMD FCH flash protections.stefanct2014-07-151-5/+8
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add Board Enable for ASUS Vintage 2 PH1 (P5LD2-MQ).stefanct2014-07-142-0/+3
| | | | | | | | | | | | ASUS Vintage 2 PH1 barebone systems have a mainboard from the P5LD2 series, namely the P5LD2-MQ (although it is labeled V2-PH1). Pin 16 GPIO needs to be raised to enable write/erase like on other boards of the series. NB: it uses a ICH7DH southbridge and hence requires different PCI IDs. Signed-off-by: Dima Veselov <kab00m@lich.phys.spbu.ru> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Improve messages on failed erases with default verbosity.stefanct2014-07-131-2/+2
| | | | | | | | | | | | | | | | | | | | | Without this... Erasing and writing flash chip... ERASE FAILED at 0x00001000! Expected=0xff, Read=0xb4, failed byte count from 0x00000000-0x0000ffff: 0xef09 ERASE FAILED! Reading current flash chip contents... done. <loooooong break while the next eraser and writing is tried> Erase/write done. Verifying flash... VERIFIED. Even if there is not a long temporal pause, it is very confusing for the user to first see a failed erase, followed by a read, a done message and eventually the verification message. This patch inserts "Looking for another erase function." where there is just a silent pause above. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix Intel FWH IDSEL message printing.stefanct2014-07-131-7/+7
| | | | | | | | | | This should get rid of extra and/or missing line breaks in verbose(+) output on Intel chipsets. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Macronix MX29F022(N)B and MX29F022(N)T.stefanct2014-07-132-0/+65
| | | | | | | | | | The MX29F022(N)T definition was successfully tested by Daniele. Signed-off-by: Daniele Forsi <dforsi@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix garbage handling in DMI strings.stefanct2014-07-131-17/+35
| | | | | | | | | | | | | | | | | | | | Previously we tried to replace garbage characters with <space> directly in the read-only memory-mapped SMBIOS area(!). This could never have worked for any DMI strings with garbage and results in a segfault on machines with such strings. Thanks to Brian Rak (Supermicro X10SLE-F) and John Pohlman (HP XW9400) for reporting this issue. With this patch the strings are duplicated within dmi_string() already, just before we sanitize them. Also, the limit variable used everywhere points to the first invalid byte address. Refine respective checks accordingly. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Macronix MX25U12835F.stefanct2014-07-131-0/+40
| | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* EEPROM support: handle implicit erasehailfinger2014-06-162-0/+6
| | | | | | | | | | | | Add support for EEPROMs with 1 byte granularity and implicit erase on write. flashrom will not try to erase before write on these chips. Explicitly requested erase with -E is done by writing 0xff. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add selfcheck_board_enables().stefanct2014-06-123-0/+35
| | | | | | | | | | | | Check for NULL termination of the array, that each board has the two main PCI ID sets defined, that coreboot vendor and model fields are either both set or unset, and that at least either an enable function or a max decode size is available. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove MCP6/7/8 SPI log requests.stefanct2014-06-121-14/+5
| | | | | | | | | | We got enough (and no one is looking at them for the time being anyway). Also, return an error code in the case no bus type could be detected. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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