| Commit message (Collapse) | Author | Age | Files | Lines |
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Details, lspci/superiotool/flashrom logs:
http://www.flashrom.org/pipermail/flashrom/2010-October/005160.html
Also add the vendor website URL for this board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Also, spelling correction.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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as the subject.
Ask people to include more information in the subject line to make life
easier for developers/supporters.
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This also adds (and marks as tested) a chipset-enable for the SiS 741.
All operations successfully tested on hardware.
lspci/superiotool:
http://www.flashrom.org/pipermail/flashrom/2010-September/004710.html
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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as tested.
Match on ethernet and north bridge.
This is tested on an OptiPlex GX1 400L+ but will probably work for
the whole GX1 series as they all share the same vendor BIOS.
lspci/flashrom output
http://www.flashrom.org/pipermail/flashrom/2010-July/004042.html
lspci output (OptiPlex GX1 unknown model)
http://www.coreboot.org/pipermail/coreboot/2010-May/058040.html
superiotool output (OptiPlex GX1 266L+)
http://www.flashrom.org/pipermail/flashrom/2009-July/000207.html
lspci/dmidecode output (OptiPlex GX1 266L+)
http://www.coreboot.org/pipermail/coreboot/2009-July/050958.html
Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Reported by Konstantin <hc@comp.susu.ac.ru>
lspci (superiotool missing, doesn't matter for this patch)
http://www.coreboot.org/pipermail/flashrom/2010-September/004609.html
DMI is needed, as there are no usefull PCI IDs.
(no test of that board yet, thus marked as untested)
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Match on Memory Controller/LPC Bridge.
lspci/superiotool output:
http://www.coreboot.org/pipermail/flashrom/2010-September/004829.html
Test report:
http://www.coreboot.org/pipermail/flashrom/2010-September/004835.html
Tested-by: Andrew Cleveland <evil.saltine@gmail.com>
Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The board-enable is the same as for the ASUS A7V8X, i.e., it raises
GP51 on the ITE IT8703F. I verified using a multimeter that this
will raise both, WE# and TBL# on the flash chip.
All operations successfully tested on hardware.
Also renamed board_asus_a7v8x() to it8703f_gpio51_raise().
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Joshua Roys <roysjosh@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1167 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Mark the following boards as tested:
- Intel Foxhollow (reported by Jason Shriver <J.Shriver@F5.com>)
http://www.flashrom.org/pipermail/flashrom/2010-September/004768.html
- Intel Greencity (reported by Jason Shriver <J.Shriver@F5.com>)
http://www.flashrom.org/pipermail/flashrom/2010-September/004768.html
- Tyan S2915-E (Thunder n6650W) (reported by Axel Bergerhoff
<axelbergerhoff@compuserve.com>)
http://www.flashrom.org/pipermail/flashrom/2010-August/004560.html
- ASUS Z8NA-D6C (reported by John Wells <jb@sourceillustrated.com>)
http://www.flashrom.org/pipermail/flashrom/2010-September/004737.html
- GIGABYTE GA-7DXR (reported by Uwe Hermann <uwe@hermann-uwe.de>)
http://www.flashrom.org/pipermail/flashrom/2010-September/004712.html
- MSI MS-7211 (PM8M3-V) (reported by Shahar Or <mightyiampresence@gmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-September/004612.html
- MSI MS-6787 (P4MAM-V/P4MAM-L) (reported by Swift Geek <swiftgeek@gmail.com>)
Board-enable now marked as tested.
http://www.flashrom.org/pipermail/flashrom/2010-September/004687.html
Chips:
- SST SST25VF016B (reported by Warren Turkal <wt@penguintechs.org>)
http://www.flashrom.org/pipermail/flashrom/2010-September/004716.html
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Tim ter Laak <timl@scintilla.utwente.nl>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I does this by setting bits 3..2 of register 0x24 on the ITE IT8707F,
while keeping bit 3 of register 0x23 set while manipulating the first
register.
AFAIK, there is no public datasheet available for this super i/o chip, but
the above is how the vendor BIOS does it. Also, registers 0x23 and 0x24 seem
to have the same meaning as on the ITE IT8710F.
Matching on NB/SB.
Tested on a P4SC-E with SST 39SF020A flash. Probe, read, erase, write
all work.
lspci/superio output:
http://www.flashrom.org/pipermail/flashrom/2010-July/004090.html
flashrom output:
http://www.flashrom.org/pipermail/flashrom/2010-August/004566.html
Many thanks to Reinder de Haan for help with reverse engineering this!
Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Matching on NB/SB. Probe, read, erase and write all work.
lspci/superiotool output:
http://www.flashrom.org/pipermail/flashrom/2010-August/004461.html
I believe that this board enable also works for MSI BX Master (MS-6163
rev:3) and perhaps also for MSI MS-6163FC (MS-6163 rev:1) but these
boards have not been tested.
Test logs for MS-6163 (rev:2):
http://www.flashrom.org/pipermail/flashrom/2010-September/004704.html
Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1160 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Match on SMBus and Audio.
lspci/superiotool/flashrom output:
http://www.flashrom.org/pipermail/flashrom/2010-September/004689.html
Signed-off-by: Joshua Roys <roysjosh@gmail.com>
Tested-by: Alexander Mikhnovets <alexander.mikhnovets@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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SiS 745 chipset + Winbond W83697HF and Winbond W49F002U flash. Probe, read,
erase and write all work.
Matching on "NB/SB" (they are integrated). Also mark SiS 745 chipset
as tested.
lspci/superiotool:
http://www.flashrom.org/pipermail/flashrom/2010-September/004705.html
Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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lspci/superiotool:
http://www.coreboot.org/pipermail/flashrom/2010-August/004436.html
This goes the safe route of adding a match for the P4P800 that does not
match the P4P800-E Deluxe which is already in. It seems quite likely that
the whole P4P800 family could use the same board enable with one generic
board enable match, though.
This match uses host bridge + audio, because all other IDs match the
P4P800-E Deluxe board, as reported in
http://www.e-monkeys.de/Everest-Bericht.txt
(no user feedback, commit as "untested")
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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lspci/superiotool:
http://www.coreboot.org/pipermail/flashrom/2010-August/004539.html
matching SMBus + Audio, because SMBus is the only core device with
usable IDs.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1156 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Marked as untested for now, as there was no response from the user.
Signed-off-by: Sergey A Lichack <shadowpilot34@gmail.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1155 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Interestingly enough, this board's enable looked more like
enable_flash_nvidia_nforce2 than enable_flash_ck804; it whacked
0x92, not 0x88. But according to the lspci, 0x92 is already 0.
Tested successfully on hardware:
http://www.flashrom.org/pipermail/flashrom/2010-August/004568.html
http://www.flashrom.org/pipermail/flashrom/2010-September/004575.html
Signed-off-by: Joshua Roys <roysjosh@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Many thanks to Michael Karcher for reverse engineering this.
lspci/superio output:
http://www.flashrom.org/pipermail/flashrom/2010-August/004475.html
Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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lspci/superiotool:
http://www.coreboot.org/pipermail/flashrom/2010-August/004440.html
Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This patch changes the intel_piix4_gpo_set() function to always check
the GENCFG and XBCS registers for the availability of the
requested GPO line before raising/lowering it and fails otherwise. It
makes no attempt to bypass the values in these configuration
registers.
The old flashrom code did consider it safe to reprogram (multiplexed)
GPO:s 22-26 without checking the value of the controlling register
(GENCFG). I do not really know why.
I have tested this patch on an Asus P2B-N (needs GPO18 low) and MSI
MS-6163 Pro (needs GPO14 high).
The information for these registers are from the Intel "82371AB
PCI-TO-ISA / IDE XCELERATOR (PIIX4)" datasheet available here:
http://www.intel.com/design/intarch/datashts/29056201.pdf
Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- There are number of boards that have board-enables in board-enable.c but
have no corresponding entry in print.c (with or without URL doesn't matter)
and thus appear neither in the "flashrom -L" list of boards nor in the
wiki output. Fix this by adding entries for them in print.c.
- abit AN-M2
- abit KN8 Ultra
- ASUS A8Jm (laptop)
- ASUS A8N (might need changing to "A8N-SLI Deluxe", see
http://www.coreboot.org/pipermail/flashrom/2009-November/000878.html)
- ASUS A8N-LA (Nagami-GL8E)
- ASUS P4B533-E
- ASUS P4S800-MX
- HP ProLiant DL165 G6
- IBASE MB899
- Intel SE440BX-2 (marked as non-working for now though, due to
http://www.coreboot.org/pipermail/flashrom/2010-July/003952.html)
- MSI MS-6577 (Xenon)
- MSI MS-7207 (K8NGM2-L)
- Fix / amend a few board names:
- Add "ProLiant" name to the "DL145 G3" (and the new "DL165 G6"), we
use such "series" names for various other boards (e.g. "Vectra" etc)
and it also helps users googling for those names.
- HP "Vectra VL400 PC" should be "Vectra VL400" really, I'm pretty sure
the "PC" is not part of the board name but simply stands for
"personal computer". Same for "Vectra VL420 SFF PC".
- Change "ASUS A8JM" to "ASUS A8Jm" as per vendor website.
- Add comments for boards which may be listed with incorrect names,
I sent out clarification requests to the list, URLs listed as comment.
- Add "Xenon" HP name to the "MSI MS-6577" OEM board.
- Fix typo in "MS-7207 (K8N GM2-L)", should be "MS-7207 (K8NGM2-L)" as
per vendor website.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Change the DMI string to only match this exact board (DMI "NAGAMI2L")
as only this one is tested.
Similar HP OEM boards might also work using this board-enable but that's
not sure and not tested. Two of those boards have DMI strings "NAGAMI"
and "NAGAMI2".
Signed-off-by: Sean Nelson <audiohacked@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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lspci/superiotool:
http://www.coreboot.org/pipermail/flashrom/2010-August/004414.html
(URL added by Michael Karcher)
Signed-off-by: Mattias Mattsson <vitplister@gmail.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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I had to use the USB controller in the board enable because all other
subsystem IDs are having vendor: Gigabyte but mostly copy the Intel
product IDs.
lspci/superiotool:
http://www.coreboot.org/pipermail/flashrom/2010-August/004420.html
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Thomas Kalka <thomas.kalka@googlemail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Fix incorrect whitespace, indentation, and coding style in some places.
- Drop '/**' Doxygen comments, we don't use Doxygen. Even if we would use
it, the comments are useless as we don't have any Doxygen markup in there.
- Use consistent vendor name spelling as per current website (NVIDIA,
abit, GIGABYTE).
- Use consistent / common format for "Suited for:" lines in board_enable.c.
- Add some missing 'void's in functions taking no arguments.
- Add missing fullstops in sentences, remove them from non-sentences (lists).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This was successfully tested by 'kai2343' on IRC.
Thanks to Michael Karcher for finding the board enable.
Signed-off-by: Joshua Roys <roysjosh@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Boards:
- ASUS M4A785TD-M EVO (reported by Mattias Mattsson <vitplister@gmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-August/004283.html
- ASUS M2N32-SLI Deluxe (reported by Mattias Mattsson <vitplister@gmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-August/004287.html
- ASUS P2E-M (reported by Mattias Mattsson <vitplister@gmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-July/004261.html
- ASUS M2N-SLI Deluxe (reported by
Kasper M. Nielsen <kasper.nielsen85@gmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-May/003015.html
- iBASE MB899 (reported by Bernhard M. Wiedemann <bernhard@lsmod.de>)
http://www.flashrom.org/pipermail/flashrom/2010-April/002953.html
Board-enable is now marked as tested.
- ASRock 939A785GMH/128M (reported by
Lennart Sauerbeck <lists@lennart.sauerbeck.org>)
http://www.flashrom.org/pipermail/flashrom/2010-August/004340.html
Chips:
- ST M50FLW080A (reported by Mattias Mattsson <vitplister@gmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-August/004287.html
- Winbond W29EE011 (reported by Mattias Mattsson <vitplister@gmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-July/004261.html
- SST SST49LF040 (reported by Mattias Mattsson <vitplister@gmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-August/004296.html
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Thanks to "Putlinuxonit" <putlinuxonit@gmail.com> for reporting
and testing.
lspci/superiotool:
http://www.coreboot.org/pipermail/flashrom/2010-August/004309.html
Signed-off-by: Joshua Roys <roysjosh@gmail.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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lspci/superiotool:
http://www.coreboot.org/pipermail/flashrom/2010-July/004172.html
Signed-off-by: David Borg <borg.db@gmail.com>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1130 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Mark the following boards as supported:
- Foxconn A6VMX (reported by Alec Wright <alecjw@member.fsf.org>)
http://www.flashrom.org/pipermail/flashrom/2010-July/004186.html
- GIGABYTE GA-8IRML (reported by Putlinuxonit <putlinuxonit@gmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-July/004175.html
Marking the board-enable as tested now.
- MSI MS-7253 (K9VGM-V) (reported by Alex <cerebro.alexiel@gmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-June/003411.html
- Soyo SY-6BA+ III (reported by Andrew Morgan <ziltro@ziltro.com>)
http://www.flashrom.org/pipermail/flashrom/2010-June/003409.html
- GIGABYTE GA-770TA-UD3 (reported by Hering <boerni@pakke.de>)
http://www.flashrom.org/pipermail/flashrom/2010-May/003267.html
- Shuttle AV11V30 (reported by
"Néstor a.k.a. DarkMan" <master_darkman@hotmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-May/003260.html
- Tyan S3992 (reported by Alessandro Gervaso <gervaso@appliedgenomics.org>)
http://www.flashrom.org/pipermail/flashrom/2010-May/003129.html
- GIGABYTE GA-MA785GMT-UD2H (reported by
Dominick Layfield <dom.layfield@gmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-May/003061.html
Mark the following chips as tested:
- ST M25P10-A (reported by Joshua Blanton <jblanton@rldrake.com>)
http://www.flashrom.org/pipermail/flashrom/2010-June/003451.html
- ST M50FLW080A (reported by Vincent Pelletier <plr.vincent@gmail.com>)
http://www.flashrom.org/pipermail/flashrom/2010-June/003410.html
Marked PROBE and READ as tested.
- SST SST39SF020A (reported by Andrew Morgan <ziltro@ziltro.com>)
http://www.flashrom.org/pipermail/flashrom/2010-June/003409.html
- AMD Am29F010A/B (reported by Andrew Morgan <ziltro@ziltro.com>)
http://www.flashrom.org/pipermail/flashrom/2010-June/003335.html
- SST SST39VF010 (reported by Tim Small <tim@buttersideup.com>)
http://www.flashrom.org/pipermail/flashrom/2010-May/003310.html
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Programmer specific functions are of absolutely no interest to any file
except those dealing with programmer specific actions (special SPI
commands and the generic core).
The new header structure is as follows (and yes, improvements are
possible):
flashchips.h flash chip IDs
chipdrivers.h chip-specific read/write/... functions
flash.h common header for all stuff that doesn't fit elsewhere
hwaccess.h hardware access functions
programmer.h programmer specific functions
coreboot_tables.h header from coreboot, internal programmer only
spi.h SPI command definitions
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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To be safe, the onboard video of the nView edition of this board has
been included in the match. If other NF-M2 editions have the same board
enable, the match should be broadened
lspci/superiotool
http://www.coreboot.org/pipermail/flashrom/2010-April/002909.html
No success report, thus committed as untested.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1109 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The SATA controller matched in the board enable is not always present
with that ID (that's the 2-port ICH9 SATA IDE controller), but (depending
on board revision/edition or BIOS settings an ICH9 SATA RAID controller
appears instead. This patches matches on the SMBus function in the
south bridge instead of the SATA controller.
Non-working board reported by: Gunter Keilholz <gunter.keilholz@googlemail.com>
lspci/superiotool:
http://www.coreboot.org/pipermail/flashrom/2010-June/003591.html
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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lspci/superiotool:
http://www.coreboot.org/pipermail/flashrom/2010-July/003889.html
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Tested-by: Alex Loktionoff <oxy-loktionoff@mail.ru>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Non-working board reported by idlogin / Putlinuxonit <putlinuxonit@gmail.com>
lspci/superiotool:
http://www.coreboot.org/pipermail/flashrom/2010-May/003330.html
No success report, so committed as untested.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1106 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Non-working board reported by: Anders Jenbo <anders@jenbo.dk>
lspci/superiotool:
http://www.coreboot.org/pipermail/flashrom/2010-June/003346.html
no success report, so committed as untested.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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lspci/superiotool:
http://www.coreboot.org/pipermail/flashrom/2010-July/003869.html
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Mattias Mattsson <vitplister@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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No response from reporter - committed as "untested".
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Tested-by: František Kučera <linux@frantovo.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Xbox running Xebian and a few other ancient systems.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Alec Wright <alecjw@member.fsf.org>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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performs LPC->Parallel translation.
Remove board enables which triggered the IT8705 write enable manually.
Change the IT87 SPI special case to cover IT87 LPC->SPI and
LPC->Parallel translation.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested on Syntax SV266A.
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested on Shuttle AK38N, all operations work fine.
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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r1063 had several issues: The PCI IDs for this board are copy/pasted from
the A8N and plain wrong for this board and the board enable is marked as
tested although it isn't. Finally the board description was slightly
wrong and the URL missing.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Constify variables where possible.
Initialize programmer-related variables explicitly in programmer_init to
allow running programmer_init from a clean state after
programmer_shutdown.
Prohibit registering programmer shutdown functions before init or after
shutdown.
Kill some dead code.
Rename global variables with namespace-polluting names.
Use a previously unused locking helper function in sst49lfxxxc.c.
This is needed for libflashrom.
Effects on the binary size of flashrom are minimal (300 bytes
shrinkage), but the data section shrinks by 4384 bytes, and that's a
good thing if flashrom is operating in constrained envionments.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Change the match for the HP DL145 G3 to avoid matching on the DL165 G6.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1064 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Sean Nelson <audiohacked@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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This patch unifies the code for different Winbond W83627-family chips,
to be applied before I add another W83627 GPIO raise function.
After the Ack I added the check for unimplemented GPIO ports, but still
dared to reuse the ack.
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Sean Nelson <audiohacked@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Fix compiler error (bad forward port in r1040).
Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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