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* Random flashrom updates:uwe2009-05-281-11/+5
| | | | | | | | | | | | | | | | | | | | | | - Add explicit installation instructions in the README. - Code cleanups, coding style fixes, drop dead code. - Drop duplicate board listings from -L output (some boards were explicitly recorded in boards_ok[] _and_ implicitly via the board-enables table. - Add MS-xxxx numbers to MSI boards where we can find that info. - Fix typo, "K8T Neo2" should have been "K8T Neo2-F" actually, at least according to the comment of w83627thf_gpio4_4_raise_2e() which says "Suited for: MSI K8T Neo2-F". Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* A bunch of flashrom board updates:uwe2009-05-281-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marked as OK: - ASUS M2V (reported by Henri Valta <henri.valta@kemi.fi>) http://www.coreboot.org/pipermail/coreboot/2009-May/048674.html - Jetway J7F4K1G5D-PB (reported by Kevin O'Connor <kevin@koconnor.net>) - PC Engines Alix.3d3 (reported by Tobias Müller <Tobias_Mueller@twam.info>) http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html - MSI K7N2 (reported by Maciej Pijanka <maciej.pijanka@gmail.com>) http://www.coreboot.org/pipermail/coreboot/2009-May/048777.html Marked as (so far) non-working: - DFI 855GME-MGF (reported by Tobias Müller <Tobias_Mueller@twam.info>) http://www.coreboot.org/pipermail/coreboot/2009-May/048549.html - ASUS M3N78 Pro (reported by Piotr Esden-Tempski <esden@esden.net>) As discussed on IRC this is an MCP78 chipset with SPI translation apparently done in the southbridge, and we have no NVIDIA datasheets, of course. So the situation for this board will probably not change anytime soon. - MSI MS-6178 (reported by Uwe Hermann <uwe@hermann-uwe.de>) I tested write/erase will not work on this board, so a write-enable is needed. In _addition_, the board immediately powers off if you hot-unplug the PLCC chip, so I guess there's some SMI interference. - GIGABYTE GA-K8N-SLI (reported by Alexander Gordeev <lasaine@lvk.cs.msu.su>) This is currently being discussed on the mailing list (see http://www.coreboot.org/pipermail/coreboot/2009-May/048717.html) and it's very likely that we'll be able to add a board-enable, so this board can be maked as OK soonish. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add NForce2 chipset enable.libv2009-05-261-1/+1
| | | | | | | | | | | | | | While the other chipset enables for nvidia could potentially also work, this one, by not touching other bits, seems like the safest solution. Uwe tested this on his Asus A7N8X Deluxe, so hopefully the A7N8X-E (reporter unknown) is now no longer an issue. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refactor SuperIO accesses. We had duplicated code under different nameshailfinger2009-05-251-46/+43
| | | | | | | | | | | | | | | | and even open-coded some functions in some places. wbsio_read/regval -> sio_read wbsio_write/regwrite -> sio_write wbsio_mask -> sio_mask board_biostar_p4m80_m4 now uses existing IT87 functions. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Luc Verhaegen <libv@skynet.be> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Biostar p4m80 board enable typo.libv2009-05-251-1/+1
| | | | | | | | | | Obvious typo due to inb/outb versus wbsio_ argument ordering confusion. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Autodetection support and write-enable for the MSI KT4 Ultra.uwe2009-05-231-3/+5
| | | | | | | | | | | | | Thanks Christian Ruppert <spooky85@gmail.com> for testing on hardware. (also: Fix a typo and some whitespace while I'm at it) Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* A bunch of output beautifications and improvements, as well as docoxygene2009-05-221-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | fixes: - Update manpage, we now report supported boards via -L. - Add some missing escaping for '-' characters in the manpage. - Shorten some of the really long device names, so that -L output looks nicer. - Display a "table header" for all entries/columns in -L output. - Make -L output tabular for all lists for better readability. - Do not print "unknown XXXX SPI chip" entries in -L output. - And random other cosmetics... Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Mark the following boards as 'known-good' (write/erase works):uwe2009-05-211-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | - ASUS P5B-Deluxe (reported by Andrew Paprocki) - ASUS P6T Deluxe V2 (reported by Aldrik Dunbar) - GIGABYTE GA-6ZMA (reported by Urja Rannikko) - Intel EP80759 (reported by Stephan GUILLOUX) - MSI MS-7345 (P35 Neo2-FIR) (reported by Onno) - MSI MS-7168 (Orion) (reported by ubuntosaure) - Supermicro H8QC8 (reported by Victor Zele) Mark the following boards as 'known-bad' (they likely require a write-enable): - Abit IS-10 (reported by deejkuba) - ASUS P5B (reported by Henning Fleddermann) - ASUS P5BV-M (reported by Bernhard M. Wiedemann) - Boser HS-6637 (reported by Mark Robinson) Also, mark the Winbond W39V040A as fully tested (report by ubuntosaure). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add detection support and write-enable for the GIGABYTE GA-MA78GM-S2H.uwe2009-05-181-1/+2
| | | | | | | | | | | | | | | | | Thanks Michael Heimann for reporting. The board was misidentified as a GIGABYTE GA-MA78G-DS3H though, as the old PCI IDs and subsystem IDs of match. Thus, use differing ones for both boards, which is not so easy. The only usable-looking difference is in the SATA controller subsystem IDs. This should allow us to properly detect both boards. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Drop duplicate Tyan S2498 (Tomcat K7M) entry in the board list (trivial).uwe2009-05-181-34/+33
| | | | | | | | | Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add Tyan S2891/S2892/S2895 as supported without special write-enablesuwe2009-05-181-0/+3
| | | | | | | | | | | being required. Thanks Myles Watson <mylesgw@gmail.com> for the report. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@532 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* List all boards which are:uwe2009-05-161-41/+122
| | | | | | | | | | | | | | | | - Supported out of the box (no flash enables required) - Verifiably not yet working (unknown flash enable) Also, move some structs to flash.h in preparation for later wiki output support. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@523 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Drop unused/duplicated #includes and some dead code (trivial).uwe2009-05-161-3/+0
| | | | | | | | | | | Build-tested on 32bit x86. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for EPoX EP-8K5A2 and separate out common VT823x board enable code.uwe2009-05-091-53/+87
| | | | | | | | | Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Split vendor name and board name into two fields as preparationuwe2009-05-091-42/+47
| | | | | | | | | | | for wiki output of supported stuff. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Keep list of boards alphabetically sorted. This is (among other things)uwe2009-05-081-20/+21
| | | | | | | | | | | | useful/required for the -L output and the upcoming wiki-syntax output of supported boards. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4161hailfinger2009-04-211-0/+2
| | | | | | | | | | | | | flashrom: Add support for Gigabyte GA-MA790FX-DQ6. This board uses IT8718F LPC->SPI translation for the flash chip. Tested by Mateusz Murawski. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Mateusz Murawski <matowy@tlen.pl> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@438 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4142stuge2009-04-201-421/+43
| | | | | | | | | | | | | | | | flashrom: board_enables: reconstruct table. This patch restores the pciid based board matching table. It makes this table readable and hackable again, and the only disadvantage is that the right margin is way beyond the rather dogmatic 80. All 0x0000 pci ids have been string replaced by 0 to more easily spot missing ids, and extra comments have been added to explain how the various entries are used. Signed-Off-By: Luc Verhaegen <libv@skynet.be> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4132stuge2009-04-171-0/+14
| | | | | | | | | | flashrom: Add VIA PC3500G board. It has SPI flash behind ITE8716 on LPC. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: illdred <illdred@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4086rminnich2009-04-091-2/+1
| | | | | | | | | | | | Fixed the typo should indeed be a 0x2e. Tested on an iWILL DK8-HTX board. Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 4031stuge2009-03-301-0/+27
| | | | | | | | | | | | | | flashrom: Board enable support for HP DL145 G3. This is a BCM5785 based machine, WP# and TLB# need to be deasserted using GPIO 2 and 5 from the PM registers of the southbridge. This is very similar to the x3455 implementation. Signed-off-by: Mondrian Nuessle <nuessle@uni-hd.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3927stuge2009-02-021-0/+22
| | | | | | | | | | flashrom: MSI MS-7046 board enable Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: David Tiemann <davidtiemann@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3911stuge2009-01-261-0/+14
| | | | | | | | | | flashrom: Intel Desktop Board D201GLY Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3909stuge2009-01-261-5/+5
| | | | | | | | | | flashrom: Export Winbond SuperIO register access functions in board_enable.c. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3861hailfinger2009-01-151-51/+362
| | | | | | | | | | | | | | | | | | | | | Similarly to flashchips array, this patch intends to make the table board_pciid_enables more readable. Signed-off-by: Stephan Guilloux <stephan.guilloux@free.fr> > What real problem does this solve? 1. Next time someone adds a new struct member, we avoid mistakes of ordering of initializers 2. we avoid mistakes in the first place. The .x = y stuff was added for a (good) reason, I think this is an improvement. Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3859stuge2009-01-121-0/+2
| | | | | | | | | | | | | | flashrom: Board enable for GIGABYTE GA-MA78G-DS3H This board has 2x MX25L8005 flash chips behind an IT8718F LPC->SPI bridge. The board uses GIGABYTE's patented BIOS failover technology, and at this point we do not know how to control which of the two chips flashrom actually hits. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Yul Rottmann <yulrottmann@bitel.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3833uwe2008-12-221-0/+3
| | | | | | | | | | | | | | | | Add another board-enable line for the Kontron 986LCD-M/mITX. There seem to be at least two versions of the board out there, and the subsystem IDs changed between the versions. Patch successfully tested on hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3669uwe2008-10-181-25/+27
| | | | | | | | | | | Coding-style fixes for flashrom, partly indent-aided (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3528uwe2008-08-191-0/+47
| | | | | | | | | | | | Add support for MSI KT4V to flashrom. The KT4V is autodetected and supports the KT3 Ultra 2 with "-m msi:kt4v" (but is not autodetected, yet). Signed-off-by: Sean Nelson <snelson@nmt.edu> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@309 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3431stuge2008-07-211-0/+8
| | | | | | | | | | | | | | | | | | flashrom: Winbond W39V040C and MSI K8T Neo2-F W39V040C does standard JEDEC commands except chip erase so add a small driver. probe_w39v040c() prints the block lock pin status when a chip is found. The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs. Many thanks to Daniel McLellan for testing all of this on hardware! Build tested by Uwe. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3413stuge2008-07-051-0/+2
| | | | | | | | | | | | | flashrom: Add PCI IDs for EPIA-CN Uses the 0.0 Host bridge CN700/VN800/P4M800CE/Pro and 11.0 ISA bridge devices with their 1106:aa08 subsystem id:s for autodetection. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3403stuge2008-07-021-1/+1
| | | | | | | | | | | | flashrom: Unknown vendor:board message can be triggered by -m too Thanks to Stefan for pointing this one out. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3402stuge2008-07-021-4/+3
| | | | | | | | | | | | | flashrom: Case insensitive matching of vendor:board strings in coreboot table Needed at least for GIGABYTE:m57sli in coreboot to match gigabyte:m57sli in flashrom. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3366stuge2008-06-131-0/+3
| | | | | | | | | | | | | flashrom: Board enable and autodetection for GIGABYTE GA-7VT600 Uses the VT8237 ISA bridge with mainboard subsystem ID and Realtek 8139 with mainboard subsystem ID for board detection. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3364stuge2008-06-111-0/+28
| | | | | | | | | | | | | | | | flashrom: Board enable and autodetection for BioStar P4M80-M4. Thanks to Reinder for clean room reverse engineering and data sheet diving! This board is autodetected because there are some good BioStar subsystem IDs. Matching uses onboard VT6420 SATA RAID with subsystem BioStar 3206 and onboard UniChrome Pro IGP graphics with subsystem BioStar 1202. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Lyos Gemini Norezel <lyos.gemininorezel@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3348uwe2008-05-221-1/+1
| | | | | | | | | | | | | | | A bunch of cosmetic improvements (trivial). - Fix typos and inconsistencies. - Drop duplicate line which tells us the chip name twice. - Also print the chip vendor, not only the name. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3346uwe2008-05-221-0/+49
| | | | | | | | | | | | | | | | | | | Add support for the ASUS P4B266 board. Tested on actual hardware. This patch add an ich_gpio_raise() function which can be re-used by other board-specific funtions which need to raise GPIOs on ICHx southbridges. This also fixes bug #7, see http://tracker.coreboot.org/trac/coreboot/ticket/7, as it turned out the ICH2 (and other ICHx) code works fine. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3344hailfinger2008-05-221-42/+42
| | | | | | | | | | | | | | Changes to make flashrom compile (and work) on FreeBSD. This patch addresses different argument order of outX() calls, FreeBSD-specific headers, difference in certain type names and system interface names, and also FreeBSD-specific way of gaining IO port access. Signed-off-by: Andriy Gapon <avg@icyb.net.ua> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3165stepan2008-03-171-0/+38
| | | | | | | | | | | | Support for the Winbond W39V080FA series of chips. Support for flashing on the Kontron 986LCD-M board. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3138uwe2008-03-131-2/+10
| | | | | | | | | | | Also print the required -m option in --list-supported output (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3133uwe2008-03-121-0/+12
| | | | | | | | | | | | Add --list-supported option to flashrom which lists the supported ROM chips, chipsets, and mainboards (Closes #90). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3110stepan2008-02-201-0/+70
| | | | | | | | | | | | | | | flashrom: Add board_enable for Artec Group DBE61 and DBE62 Also add a comment about NULL subsystem IDs leaving the board entry out of auto-detection logic. Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee> Acked-by: Luc Verhaegen <libv@skynet.be> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3099hailfinger2008-02-091-1/+25
| | | | | | | | | | | Flashrom: Add board enable for VIA EPIA SP. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3082stuge2008-01-271-3/+19
| | | | | | | | | | | | Make the vendor name optional in the -m flashrom parameter when there's only one board name that matches. The full syntax still works, and is required when two vendors have boards with the same names. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3054stepan2008-01-181-5/+5
| | | | | | | | | | | for some reasons the externals did not get committed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@178 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 3033rminnich2008-01-041-0/+2
| | | | | | | | | Add board enable for the gigabyte ga_2761gxdk board Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 2997uwe2007-12-041-39/+37
| | | | | | | | | | | | | | Various coding style fixes, constification, fixed typos (trivial). Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 2995uwe2007-12-021-0/+28
| | | | | | | | | | | | Add board-enable for Acorp 6A815EPD. Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 2873uwe2007-10-171-5/+5
| | | | | | | | | | | Some cosmetic cleanups in the flashrom code and output. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Original v2 revision: 2864hailfinger2007-10-161-0/+2
| | | | | | | | | | | Add Gigabyte M61P-S3 SPI flash support to board_enable.c Signed-off-by: Michael van der Kolff <mvanderkolff@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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