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* Revert PCI config space writes on shutdown.hailfinger2010-11-101-45/+33
* A lot of messages sent to flashrom@flashrom.org just have "flashrom -V"hailfinger2010-10-081-3/+8
* Remove duplicate includes from the code.stepan2010-10-061-1/+0
* Add a board-enable for the ASRock K7S41, chipset-enable for SiS 741.uwe2010-10-051-0/+1
* Add chipset enable for Broadcom OSB4.hailfinger2010-09-151-0/+18
* Add a board enable for MSI MS-6561 (745 Ultra).uwe2010-09-111-1/+1
* Add support for Intel 5 Series / 3400 Series chipsetsmkarcher2010-08-111-0/+14
* Various cosmetic and coding-style fixes (trivial).uwe2010-08-081-3/+3
* Add support for SIS661 (SIS963).hailfinger2010-07-311-0/+1
* Add Nvidia nForce MCP61/MCP65/MCP67/MCP78S/MCP73/MCP79 SPI flashinghailfinger2010-07-281-146/+39
* Split off programmer.h from flash.h.hailfinger2010-07-271-0/+1
* Convert all PCI-based external programmers to use special little-endianhailfinger2010-07-271-2/+2
* Move SB600 SPI initialization to sb600spi.cmkarcher2010-07-221-77/+5
* Move Intel SPI initialisation to ichspi.cmkarcher2010-07-221-200/+18
* Fix out-of-bounds ICH FREG permission printing. A bit was masked, buthailfinger2010-07-131-3/+4
* Make programmer_param static by converting all users tohailfinger2010-07-081-1/+1
* Various places in the flashrom source feature custom parameterhailfinger2010-07-061-5/+10
* Kill global variables, constants and functions if local scope suffices.hailfinger2010-07-031-30/+30
* ICH9/10: display FRAP/FREGx access controlshailfinger2010-07-011-15/+47
* Kill unneeded #include wherever possible.hailfinger2010-06-211-3/+1
* Fill in buses_supported for remaining Intel chipsets (ICH0-ICH5,hailfinger2010-06-201-0/+2
* VIA: disable byte mergingmkarcher2010-06-131-7/+52
* Board-enable for MS-7025 (K8N Neo2 Platinum)mkarcher2010-06-121-0/+1
* Remove unneeded #include statements completely.hailfinger2010-05-301-0/+1
* ICH SPI can enforce address restrictions for all accesses which take anhailfinger2010-05-281-4/+4
* Handle the following architectures in generic flashrom code:hailfinger2010-05-261-1/+6
* Add debug output of the exact matched chipset PCI ID to keep track ofhailfinger2010-05-221-0/+3
* Fix Tyan S2915 OEM board by commenting out MCP55 LPC bridge PCI IDhailfinger2010-05-221-1/+9
* convert programmer print messages to msg_p*snelson2010-05-071-108/+108
* Rename identifiers called 'byte'mkarcher2010-02-251-14/+14
* Refactor MCP SPI detection:hailfinger2010-02-181-54/+101
* Add SPI mode diagnostics for all post-MCP55 (nForce 5) chipsets fromhailfinger2010-02-131-1/+137
* Add Intel NM10 chipset enable.hailfinger2010-01-191-0/+1
* Don't use "byte" as identifier.mkarcher2010-01-121-11/+11
* Chipset: Fix sis5x0 register write verification.libv2010-01-101-13/+3
* Fix Intel FWH decode sizemkarcher2010-01-031-2/+2
* Add VIA VT8233A identification, mark as tested.hailfinger2009-12-231-0/+1
* Chipset/Board: vt8237: Set All mem cycles to LPC in chipset enable.libv2009-12-231-0/+7
* Chipset: Add support for Intel Poulsbo chipset.libv2009-12-211-0/+22
* Use the maximum decode size infrastructure.hailfinger2009-12-171-27/+96
* Internal (onboard) programming was the only feature which could not behailfinger2009-12-131-21/+0
* Chipset: remove sis630 chipset enable for sis540.libv2009-12-091-51/+17
* Intel PIIX* chipsets only support parallel flash (no LPC/FWH/SPI).uwe2009-12-081-0/+2
* Add support for Intel 3400 series / 5 series chipset.hailfinger2009-11-261-0/+3
* Mark Elitegroup K7S5A as supported.hailfinger2009-11-151-28/+28
* Add support for every single SiS chipset out there.hailfinger2009-11-151-67/+200
* Add infrastructure to check and report to the user the maximum supportedhailfinger2009-10-311-0/+11
* Mark NVIDIA Nforce4/MCP04 as tested.libv2009-10-061-1/+1
* Chipset support for the nVidia nForce 4.libv2009-10-051-0/+1
* Add chipset support for VIA VT82C596 by adding a PCI ID (trivial).uwe2009-09-251-0/+1
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