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* whitespace, documentation and other small stuffstefanct2011-05-191-2/+2
| | | | | | | | | | | | | | | this patch combines three previously posted patches in a revised form. one is even stolen from Stefan Reinauer (remove umlauts from man page). Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Signed-off-by: Stefan Reinauer <reinauer@google.com> some parts are Acked-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006@gmx.net> the rest is Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Via VX855 chipsetmkarcher2011-05-051-0/+1
| | | | | | | Signed-off-by: John Schmerge <jbschmerge@gmail.com> for Devon IT Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* List AMD SB850 as supported (it has the same PCI ID as SB700).hailfinger2011-04-021-1/+1
| | | | | | | | | | | Success report at http://flashrom.org/pipermail/flashrom/2011-March/006072.html Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix typo in chipset_enable.cstepan2011-03-291-1/+1
| | | | | | | | | Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* flashrom: fix sparse warning: Using plain integer as NULL pointerstepan2011-01-241-1/+1
| | | | | | | | | | | | | This patch fixes the "using plain integer as NULL pointer" warnings generated by running sparse on the flashrom source. Signed-off-by: Peter Huewe <peterhuewe@gmx.de> Acked-by: Mathias Krause <mathias.krause@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix decoding of SB600 LPC ROM protection registers.krause2011-01-011-6/+6
| | | | | | | | | | | The address part was using a bit of the size, the size was missing the upper bit, was off by 1023 bytes and included the protection bits. Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Revert PCI config space writes on shutdown.hailfinger2010-11-101-45/+33
| | | | | | | | | | | | | | | | This means all chipset enables etc. will be undone on shutdown. Reversible PCI config space writes now use rpci_write_*(). PCI config space writes which are one-shot (e.g. communication via config space) should continue to use the permanent pci_write_* variants. Extend the number of available register_shutdown slots to 32. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* A lot of messages sent to flashrom@flashrom.org just have "flashrom -V"hailfinger2010-10-081-3/+8
| | | | | | | | | | | | as the subject. Ask people to include more information in the subject line to make life easier for developers/supporters. Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove duplicate includes from the code.stepan2010-10-061-1/+0
| | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a board-enable for the ASRock K7S41, chipset-enable for SiS 741.uwe2010-10-051-0/+1
| | | | | | | | | | | | | | | | This also adds (and marks as tested) a chipset-enable for the SiS 741. All operations successfully tested on hardware. lspci/superiotool: http://www.flashrom.org/pipermail/flashrom/2010-September/004710.html Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add chipset enable for Broadcom OSB4.hailfinger2010-09-151-0/+18
| | | | | | | | | | No docs available. Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1174 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a board enable for MSI MS-6561 (745 Ultra).uwe2010-09-111-1/+1
| | | | | | | | | | | | | | | | | | SiS 745 chipset + Winbond W83697HF and Winbond W49F002U flash. Probe, read, erase and write all work. Matching on "NB/SB" (they are integrated). Also mark SiS 745 chipset as tested. lspci/superiotool: http://www.flashrom.org/pipermail/flashrom/2010-September/004705.html Signed-off-by: Mattias Mattsson <vitplister@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Intel 5 Series / 3400 Series chipsetsmkarcher2010-08-111-0/+14
| | | | | | | | | | | (At least) for the QM57 which i have tested an additional patch was needed as some reserved bits in the "Software Sequencing Flash Control Register" (SSFC) needs to be programmed to 1 in the QM57. Signed-off-by: Helge Wagner <helge.wagner@ge.com> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1137 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Various cosmetic and coding-style fixes (trivial).uwe2010-08-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | - Fix incorrect whitespace, indentation, and coding style in some places. - Drop '/**' Doxygen comments, we don't use Doxygen. Even if we would use it, the comments are useless as we don't have any Doxygen markup in there. - Use consistent vendor name spelling as per current website (NVIDIA, abit, GIGABYTE). - Use consistent / common format for "Suited for:" lines in board_enable.c. - Add some missing 'void's in functions taking no arguments. - Add missing fullstops in sentences, remove them from non-sentences (lists). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for SIS661 (SIS963).hailfinger2010-07-311-0/+1
| | | | | | | | | | Tested on Asus P4S800-MX. Signed-off-by: David Borg <borg.db@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add Nvidia nForce MCP61/MCP65/MCP67/MCP78S/MCP73/MCP79 SPI flashinghailfinger2010-07-281-146/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | support. Huge thanks go to Michael Karcher for reverse engineering the interface and to Johannes Sjölund for testing the first iterations of my patch on his hardware until it worked. Thanks to the following testers of the patch: * MCP61, 10de:03e0, LPC OK, ECS Geforce6100SM-M, Andrew Cleveland * MCP61, 10de:03e0, LPC OK, Biostar NF520-A2 NF61D-A2, Vitaliy Buchynskyy * MCP65, 10de:0441, SPI OK, MSI MS-7369 K9N Neo-F v2, Kjell Braden * MCP65, 10de:0441, SPI OK, MSI MS-7369, Wolfgang Schnitker * MCP65, 10de:0441, SPI OK, MSI MS-7369, Johannes Sjölund * MCP65, 10de:0441, SPI OK, MSI MS-7369, Melchior Franz * MCP78S, 10de:075c, SPI OK, Asus M3N78 PRO, Brad Rogers * MCP78S, 10de:075c, SPI OK, Asus M3N78-VM, Marcel Partap * MCP78S, 10de:075c, SPI OK, Asus M4N78 PRO, Kimmo Vuorinen * MCP78S, 10de:075c, SPI OK, Asus M4N78 PRO, Vikram Ambrose * MCP79, 10de:0aad, SPI OK, Acer Aspire R3600, Andrew Morgan * MCP79, 10de:0aae, LPC ??, Lenovo Ideapad S12 laptop, Christian Schmitt * MCP79, 10de:0aae, SPI OK, Apple iMac9,1 Mac-F2218EA9, David "dledson" flashrom will refuse to write/erase for safety reasons if MCP6x/MCP7x SPI is detected. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Split off programmer.h from flash.h.hailfinger2010-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h header from coreboot, internal programmer only spi.h SPI command definitions Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert all PCI-based external programmers to use special little-endianhailfinger2010-07-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | accessors for all MMIO regions of PCI devices. This patch does _not_ touch the internal programmer (which is PCI-based as well). Huge thanks go to Misha Manulis who worked with me to create a first version of this patch for the satasii programmer based on modification of generic code. Huge thanks also go to Segher Boessenkool for suggesting the pci_mmio_ prefix for the abstraction layer. NOTE to package maintainers: With this patch, compilation and usage of flashrom should be safe on x86, x86_64, MIPS (little and big endian) and PowerPC (big endian). The internal programmer is disabled on non-x86/x86_64 (but it compiles). The atahpt, nic3com, nicnatsemi, nicrealtek and rayer_spi can not be compiled on non-x86/x86_64 because port space I/O is not (yet) supported. Please compile with default settings on x86/x86_64 and with the following settings on all other architectures: make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no CONFIG_NICNATSEMI=no CONFIG_RAYER_SPI=no Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move SB600 SPI initialization to sb600spi.cmkarcher2010-07-221-77/+5
| | | | | | | Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move Intel SPI initialisation to ichspi.cmkarcher2010-07-221-200/+18
| | | | | | | | | | | Smarter version could decide whether SPI is vital or not depending on straps. Straps are currently implemented for ICH7. EP80579 is in the comment, PCH of 5 Series/3400 Series has "LPC, reserved, PCI, SPI". Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix out-of-bounds ICH FREG permission printing. A bit was masked, buthailfinger2010-07-131-3/+4
| | | | | | | | | | | | | | | not shifted, and that led to worst-case accesses of index 24 in an array with 4 members. I've improved readability in the variable declaration block as well. Thanks to Stephen Kou for reporting the bug. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stephen Kou <stephen@hyarros.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make programmer_param static by converting all users tohailfinger2010-07-081-1/+1
| | | | | | | | | | | | extract_programmer_param. Programmer parameters can no longer be separated with a colon, they have to be separated with a comma. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Various places in the flashrom source feature custom parameterhailfinger2010-07-061-5/+10
| | | | | | | | | | | | | | | | | | | | extraction from programmer_param. This led to wildly differing syntax for programmer parameters, and it also voids pretty much every assumption you could make about programmer_param. The latter is a problem for libflashrom. Use extract_param everywhere, clean up related code and make it more foolproof. Add two instances of exit(1) where we have no option to return an error. Remove six instances of exit(1) where returning an error was possible. WARNING: This changes programmer parameter syntax for a few programmers! Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Kill global variables, constants and functions if local scope suffices.hailfinger2010-07-031-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | Constify variables where possible. Initialize programmer-related variables explicitly in programmer_init to allow running programmer_init from a clean state after programmer_shutdown. Prohibit registering programmer shutdown functions before init or after shutdown. Kill some dead code. Rename global variables with namespace-polluting names. Use a previously unused locking helper function in sst49lfxxxc.c. This is needed for libflashrom. Effects on the binary size of flashrom are minimal (300 bytes shrinkage), but the data section shrinks by 4384 bytes, and that's a good thing if flashrom is operating in constrained envionments. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ICH9/10: display FRAP/FREGx access controlshailfinger2010-07-011-15/+47
| | | | | | | | Signed-off-by: Joshua Roys <roysjosh@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1066 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Kill unneeded #include wherever possible.hailfinger2010-06-211-3/+1
| | | | | | | | | | | Tested on Linux, FreeBSD, NetBSD, OpenBSD, DOS. Thanks to Jonathan A. Kollasch and Idwer Vollering for testing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Idwer Vollering <vidwer+lists.flashrom@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fill in buses_supported for remaining Intel chipsets (ICH0-ICH5,hailfinger2010-06-201-0/+2
| | | | | | | | | | Poulsbo). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* VIA: disable byte mergingmkarcher2010-06-131-7/+52
| | | | | | | | | | | | | | | | All mentioned north bridges have been checked against data sheet. That's all north bridges google found a datasheet for with "byte merge" included. Runs multiple chipset enables if the first one requests further enables to be run. VIA byte-merging logic tested: works. multiple chipset logic: completely untested Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1043 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Board-enable for MS-7025 (K8N Neo2 Platinum)mkarcher2010-06-121-0/+1
| | | | | | | | | | | test report is http://www.coreboot.org/pipermail/flashrom/2010-April/002967.html Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Tested-by: Valentine "Pegasus rider" Yatsenko <mr.qweo@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove unneeded #include statements completely.hailfinger2010-05-301-0/+1
| | | | | | | | | | | | | | | | unistd.h was only used to get a definition of NULL in all files. Add our own NULL #define and remove unistd.h from flash.h stdio.h has no place in flash.h, it should be included only in files which really need it. Add #include statements in individual .c files where needed. Replace a few printf with msg_* to eliminate the need for stdio.h. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ICH SPI can enforce address restrictions for all accesses which take anhailfinger2010-05-281-4/+4
| | | | | | | | | | | | | | | address (well, it could if the chipset implementation was not broken). Since exploiting the broken implementation is harder than conforming to the address restrictions wherever possible, conform to the address restrictions instead. This patch eliminates a lot of transaction errors people were seeing on chip probe. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Handle the following architectures in generic flashrom code:hailfinger2010-05-261-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian) No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them. Compilation should work on all architectures listed above for all drivers except nic3com and nicrealtek which require PCI Port IO which is x86-only for now. To compile without nic3com and nicrealtek, run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no Thanks to Misha Manulis for testing early versions of this patch on PowerPC (big endian) with the satasii programmer. Thanks to Segher Boessenkool for design review and for helping out with compiler tricks and pointing out that we need eieio on PowerPC. Thanks to Vladimir Serbinenko for compile testing on MIPS (little endian) and PowerPC (big endian) and for runtime testing on MIPS (little endian). Thanks to David Daney for compile testing on MIPS (big endian). Thanks to Uwe Hermann for compile and runtime testing on x86_64. DO NOT RUN FLASHROM ON NON-X86 AFTER APPLYING THIS PATCH! This patch only provides the infrastructure, but does not convert any drivers, so flashrom will compile, but it won't do the right thing on non-x86 platforms. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Segher Boessenkool <segher@kernel.crashing.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add debug output of the exact matched chipset PCI ID to keep track ofhailfinger2010-05-221-0/+3
| | | | | | | | | | | | tested PCI IDs for chipsets with one name and multiple IDs. This will help avoid problems similar to the Tyan S2915 OEM undetected flash in the future. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix Tyan S2915 OEM board by commenting out MCP55 LPC bridge PCI IDhailfinger2010-05-221-1/+9
| | | | | | | | | | | | | | | | | 10de:0361 which is the secondary LPC bridge. The same effect could be achieved by refusing to run enable_flash_mcp55 if the device class is not ISA bridge [0601]. Thanks to Alessandro Polverini, Joel Robertson, Nicolas Aveline, Phil LoCascio and Nils-Helge Garli Hegvik for testing flashrom on hardware and Michael Karcher for analyzing the factory BIOS for clues. In the end, no board enable was needed and it was a pure chipset issue. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* convert programmer print messages to msg_p*snelson2010-05-071-108/+108
| | | | | | | | | | | | convert general print messages to msg_g* a few fixes as suggested by Carl-Daniel Signed-off-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rename identifiers called 'byte'mkarcher2010-02-251-14/+14
| | | | | | | | | | | | Still fallout of adding "-Wshadow". Missed the ht1000 one (chipset_enable is not compied on Windows where we had the collision with "byte" last time) and the other occurrence is newly introduced. Old libpci defines a global symbol called "byte" too. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@913 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refactor MCP SPI detection:hailfinger2010-02-181-54/+101
| | | | | | | | | | | | | - Set supported buses based on ISA bridge reg 0x8a - Use MCP55 chipset enable only if LPC is detected - Allow LPC on MCP61 - Eliminate duplicated code where possible Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@906 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add SPI mode diagnostics for all post-MCP55 (nForce 5) chipsets fromhailfinger2010-02-131-1/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nvidia. Huge thanks to Michael Karcher for reverse engineering the MCP67 chipset and writing a spec. Due to this, we were able to use the chinese wall technique for 100% clean room reverse engineering. This patch doesn't touch any of the new registers, it only reads them. Assuming that read has no side effects, this patch is a no-op and safe. We need "flashrom -V" output from all post-MCP55 (nForce 5) chipset boards. Please indicate if your board uses SPI flash or LPC flash (if you know it). Note: That output is only helpful if it is created with patched flashrom and if is from the first run of flashrom after a cold boot (reset or Ctrl-Alt-Del is not sufficient). There is a pattern based on which we can probably detect which flash type is present on the board. Thanks to Alessandro Polverini for testing earlier iterations of this patch. Note: The MCP67 should work. I guessed that the other recent Nvidia chipsets would work in a similar way, and created a simplified do-nothing catchall chipset enable function which dumps some info and instructs the user to send more info. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add Intel NM10 chipset enable.hailfinger2010-01-191-0/+1
| | | | | | | | | | | | | | Public chipset documentation available at http://www.intel.com/Assets/PDF/datasheet/322896.pdf Tested on NM10-based customer reference board from Intel. Signed-off-by: David Hendricks <dhendrix@google.com> Acked-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Don't use "byte" as identifier.mkarcher2010-01-121-11/+11
| | | | | | | | | | Some mingw declares a global identifier "byte", causing -Werror -Wshadow to break compilation. This patch renames all identifiers called "byte". Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Chipset: Fix sis5x0 register write verification.libv2010-01-101-13/+3
| | | | | | | | | | | Also remove separate sis 5596 routine: superio code will be handled separately, which then turns this routine into the sis 5511 chipset enable. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix Intel FWH decode sizemkarcher2010-01-031-2/+2
| | | | | | | | | Fixes wrong detection of area decoded to the FWH interfaces. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add VIA VT8233A identification, mark as tested.hailfinger2009-12-231-0/+1
| | | | | | | | Signed-off-by: Raúl Soriano <GatoLoko@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Chipset/Board: vt8237: Set All mem cycles to LPC in chipset enable.libv2009-12-231-0/+7
| | | | | | | | | | | | | | | | | | | | | | | Only done for VT8237R (possibly needed for VT8237 too), VT8235 does not need this (even if the original bios does so: Asus A7V8X-MX SE, MSI KT4V were verified). This then opens a floodgate of cleanups in the board enables. * EPIA SP board enable vanishes, taking EPIA CN match with it. * Asus A7V8X-MX/Tyan S2498 board enable then equals w836xx_memw_enable_2e * AOpen vKM400Am-S board enable then equals it8705_rom_write_enable * Epia M board enable becomes via_vt823x_gpio15_raise * Epia N board enable becomes via_vt823x_gpio9_raise * Asus M2V-MX board enable becomes via_vt823x_gpio5_raise * vt823x_gpio_set becomes via_vt823x_gpio_set, and now detects ISA bridge itself, in concordance with intel ich and nvidia mcp gpio. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Chipset: Add support for Intel Poulsbo chipset.libv2009-12-211-0/+22
| | | | | | | Signed-off-by: Adam Jurkowski <adam.jurkowski@kontron.pl> Acked-by: Luc Verhaegen <libv@skynet.be> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use the maximum decode size infrastructure.hailfinger2009-12-171-27/+96
| | | | | | | | | | | | | | | | | | | - Detect max FWH size for Intel 631xESB/632xESB/3100/ICH6/ICH7/ICH8/ICH9/ICH10. - Move IDSEL override before decode size checking for the chipsets listed above or flashrom will complain based on old values. - Adjust supported flash buses for the chipsets listed above (none of them supports LPC or Parallel). - Detect max parallel size for AMD/National Semiconductor CS5530. - Adjust supported flash buses for CS5530/CS5530A. - Set board-specific max decode size for Elitegroup K7VTA3. - Set board-specific max decode size for Shuttle AK38N. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Internal (onboard) programming was the only feature which could not behailfinger2009-12-131-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | disabled. Make various pieces of code conditional on support for internal programming. Code shared between PCI device programmers and onboard programming is now conditional as well. It is now possible to build only with dummy support: make CONFIG_INTERNAL=no CONFIG_NIC3COM=no CONFIG_SATASII=no CONFIG_DRKAISER=no CONFIG_SERPROG=no CONFIG_FT2232SPI=no This allows building for a specific use case only, and it also facilitates porting to a new architecture because it is possible to focus on highlevel code only. Note: Either internal or dummy programmer needs to be compiled in due to the current behaviour of always picking a default programmer if -p is not specified. Picking an arbitrary external programmer as default wouldn't make sense. Build and runtime tested in all 1024 possible build combinations. The only failures are by design as mentioned above. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Chipset: remove sis630 chipset enable for sis540.libv2009-12-091-51/+17
| | | | | | | | | | | | | SiS630 chipset enable is equal to sis540 plus superio "poking". Superio poking equals IT8705F flash write enable, which is currently dealt with on a board by board basis in board_enable.c. Not all 630 and newer based boards come with it8705/sis950 superios. Signed-off-by: Luc Verhaegen <libv@skynet.be> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Intel PIIX* chipsets only support parallel flash (no LPC/FWH/SPI).uwe2009-12-081-0/+2
| | | | | | | | | Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Intel 3400 series / 5 series chipset.hailfinger2009-11-261-0/+3
| | | | | | | | | | | | | | | | Found in Intel document 322170 (Intel 5 Series Chipset and Intel 3400 Series Chipset Specification Update). According to http://pciids.sourceforge.net/ we probably should match all IDs from 0x3b00-0x3b1f, but so far I didn't find an Intel doc saying the same. If anybody has contacts at Intel and can check, I'd be happy to add the rest of the IDs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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