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That's necessary to use bulk transfers, and just the
right thing in any case.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Speed up reads by a factor of 4 by switching block size from 4 to 16.
Add support for 4 byte RDID.
Add USB error decoding via usb_strerror.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Reverse engineered from USB logs. I never touched that programmer nor
did I ever see the associated software.
Disabled by default until it is complete. The driver needs to be hooked
up to the SPI core before it will do anything besides init and
diagnostics.
I successfully reverse engineered all commands, but some are still
somewhat magic.
Logs from "flashrom -p dediprog -V" are appreciated.
Probe and read should work, erase/write is expected to explode.
The programmer will set voltage to 0 on exit.
Thanks a lot to Stefan Reinauer and Patrick Georgi for providing USB
logs and for testing the result.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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