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* Add voltage ranges to the flashchipsstefanct2011-06-031-0/+4
| | | | | | | | Signed-off-by: Steven Zakulec <spzakulec@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* small fixesstefanct2011-05-281-0/+2
| | | | | | | | | | | - missing spaces in code and output - improved documentation/naming/output - missing line breaks in spi probing functions Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* whitespace, documentation and other small stuffstefanct2011-05-191-0/+5
| | | | | | | | | | | | | | | this patch combines three previously posted patches in a revised form. one is even stolen from Stefan Reinauer (remove umlauts from man page). Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Signed-off-by: Stefan Reinauer <reinauer@google.com> some parts are Acked-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006@gmx.net> the rest is Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Constify flashchips array.hailfinger2011-05-041-2/+2
| | | | | | | | | | This moves 99.5% of the .data section to .rodata (which ends up in .text). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch reduces the stack usage by declaring 'const' stack variableskrause2011-01-171-1/+1
| | | | | | | | | | | | | | as 'static const' so they end up in the .rodata section instead of being copied from there to the stack for every invocation of the corresponding function. As a plus we end up in having a smaller binary as the "copy from .rodata to stack" code isn't emitted by the compiler any more (roughly -100 bytes). Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support setting the Dediprog SF100 SPI voltage.hailfinger2010-11-091-0/+1
| | | | | | | | | | | | Add a generic voltage parameter parser. Move tolower_string() from dummyflasher.c to flashrom.c to make it available everywhere. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add SPI flash emulation capability to the dummy programmer.hailfinger2010-11-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | You have to choose between - no emulation - ST M25P10.RES SPI flash chip (RES, page write) - SST SST25VF040.REMS SPI flash chip (REMS, byte write) - SST SST25VF032B SPI flash chip (RDID, AAI write) Example usage: flashrom -p dummy:emulate=SST25VF032B Flash image persistence is available as well. Example usage: flashrom -p dummy:image=dummy_simulator.rom Allow setting the max chunksize for page write with the dummy programmer. Example usage: flashrom -p dummy:spi_write_256_chunksize=5 Flash emulation is compiled in by default. This code helped me find and fix various bugs in the SPI write code as well as in the testsuite. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a reset to probe_jedec before we read the Chip's IDs.hailfinger2010-10-201-0/+1
| | | | | | | | | | | | | | | | | | | Previous probes might have had too short delays for entering ID mode, so the chip may still be in the process of entering the ID mode. Due to that, an additional delay before the reset makes sense. Add FEATURE_RESET_MASK to deal cleanly with those feature bits. Maciej Pijanka tested the patch and it fixes probing for him with some old Atmel chips. Signed-off-by: Sean Nelson <audiohacked@gmail.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Anders Juel Jensen <andersjjensen@gmail.com> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Always read the flash chip before writing. This will allow flashrom tohailfinger2010-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | skip erase of already-erased blocks and to skip write of blocks which already have the wanted contents. Avoid emergency messages by checking if the chip contents after a failed write operation (erase/write) are unchanged. Keep the emergency messages after a failed pure erase. That part is debatable because if someone wants erase, he pretty sure doesn't care about the flash contents anymore. Please note that this introduces additional overhead of a full chip read before write. This is frowned upon by people with slow programmers. A followup patch will make this configurable. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Switch all flash chips to partial write.hailfinger2010-10-131-1/+1
| | | | | | | | | | | | | | | | The inner write functions which handle partial write are renamed to the original name of their wrappers. The write wrappers are removed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Tested-by: Andrew Morgan <ziltro@ziltro.com> Tested-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Idwer Vollering <vidwer@gmail.com> Tested-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* SPI write status register (WRSR) may take longer than 100 ms, and ithailfinger2010-10-081-0/+3
| | | | | | | | | | | makes sense to poll for completion in 10 ms steps until 5 s are over. This patch complements r1115. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Joshua Roys <roysjosh@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* flashrom -L output did not contain a list of programmers nor were allhailfinger2010-10-061-0/+1
| | | | | | | | | | | | programmers listed. Fix it and mention at least the name of each programmer. Wiki output is unchanged, and will need separate fixups. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Implement libpayload support and improve life for DOShailfinger2010-09-251-0/+2
| | | | | | | | | | | | | | | | | based flashrom, too: Change the physmap* behaviour to use (void*)-1 as error code instead of NULL. That way, 1:1 mapped memory can be supported properly because (void*)0 is not a magic pointer anymore. (void*)-1 on the other hand is a rather unlikely memory offset, so that should be safe. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add detailed status register printing and unlocking for all ATMEL AT25*hailfinger2010-07-291-1/+5
| | | | | | | | | | | | | | | | | chips. Add support for Atmel AT25DF081A and AT25DQ161. Some chips require EWSR before WRSR, others require WREN before WRSR, and some support both variants. Add feature_bits to select the correct SPI command, and default to EWSR. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Steven Rosario Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Split off programmer.h from flash.h.hailfinger2010-07-271-525/+0
| | | | | | | | | | | | | | | | | | | | | | Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h header from coreboot, internal programmer only spi.h SPI command definitions Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert all PCI-based external programmers to use special little-endianhailfinger2010-07-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | accessors for all MMIO regions of PCI devices. This patch does _not_ touch the internal programmer (which is PCI-based as well). Huge thanks go to Misha Manulis who worked with me to create a first version of this patch for the satasii programmer based on modification of generic code. Huge thanks also go to Segher Boessenkool for suggesting the pci_mmio_ prefix for the abstraction layer. NOTE to package maintainers: With this patch, compilation and usage of flashrom should be safe on x86, x86_64, MIPS (little and big endian) and PowerPC (big endian). The internal programmer is disabled on non-x86/x86_64 (but it compiles). The atahpt, nic3com, nicnatsemi, nicrealtek and rayer_spi can not be compiled on non-x86/x86_64 because port space I/O is not (yet) supported. Please compile with default settings on x86/x86_64 and with the following settings on all other architectures: make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no CONFIG_NICNATSEMI=no CONFIG_RAYER_SPI=no Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix compilation for CONFIG_INTERNAL=nomkarcher2010-07-241-0/+6
| | | | | | | | | broken by r1098 Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move SB600 SPI initialization to sb600spi.cmkarcher2010-07-221-1/+1
| | | | | | | Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move Intel SPI initialisation to ichspi.cmkarcher2010-07-221-3/+6
| | | | | | | | | | | Smarter version could decide whether SPI is vital or not depending on straps. Straps are currently implemented for ICH7. EP80579 is in the comment, PCH of 5 Series/3400 Series has "LPC, reserved, PCI, SPI". Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for RayeR SPIPGM hardware as described inhailfinger2010-07-211-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://rayer.ic.cz/elektro/spipgm.htm To use the RayeR driver, run flashrom -p rayer_spi -V Known bugs/limitations: - Won't compile/work on non-x86 architectures. - Will always use direct port I/O access. Log follows: flashrom v0.9.2-r1039 on MS-DOS 7 (i686), built with libpci 3.1.5, GCC 4.3.2, little endian Calibrating delay loop... OK. Initializing rayer_bitbang_spi programmer Using port 0x378 as I/O base for parallel port access. ... Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 ... Found chip "Macronix MX25L1605" (2048 KB, SPI) at physical address 0xffe00000. ... No operations were specified. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Martin Rehak <rayer@seznam.cz> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Check during SPI bitbang init that SPI bitbang master configuration ishailfinger2010-07-181-1/+1
| | | | | | | | | | correct. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use struct pointer instead of enum to set bitbang adaptermkarcher2010-07-171-5/+6
| | | | | | | Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Change the SPI bitbanging core to fix a subtle bug (which had no effecthailfinger2010-07-171-5/+1
| | | | | | | | | | | | | | | | so far) and to make integration of the RayeR SPIPGM and Nvidia MCP6x/MCP7x SPI patches easier. Kill a few global variables and require explicit initialization of bitbanging delay. A big thank you to Johannes Sjölund for testing an earlier version of the code as part of the Nvidia MCP6x/MCP7x SPI bitbanging patch. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use the max_rom_decode infrastructure for wbsio_spi instead ofhailfinger2010-07-141-1/+0
| | | | | | | | | | open-coding a variant which only aborts after it is too late. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1081 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert SPI chips to partial write, but wrap the write functions in ahailfinger2010-07-141-8/+9
| | | | | | | | | | | | | | compat layer to allow converting the rest of flashrom later. I actually have patches for most of the remaining conversion, but I wanted to get this out and reviewed first. Tested on Intel NM10 by David Hendricks. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Print an error message on read errors and abort instead of proceedinghailfinger2010-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | anyway. Improve error checking in file write, chip read and chip verify. Refactor the read routines a bit to split reading from file writing. Log for a failed read: [...] Found chip "Winbond W25x16" (2048 KB, SPI) at physical address 0xffe00000. Reading flash... Invalid OPCODE 0x03 Read operation failed! FAILED. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-By: Stephen Kou <stephen@hyarros.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1079 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Autodetect the ITE IT8705 Super I/O and enable flash writes if ithailfinger2010-07-101-2/+2
| | | | | | | | | | | | | | | | | | performs LPC->Parallel translation. Remove board enables which triggered the IT8705 write enable manually. Change the IT87 SPI special case to cover IT87 LPC->SPI and LPC->Parallel translation. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested on Syntax SV266A. Acked-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested on Shuttle AK38N, all operations work fine. Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make programmer_param static by converting all users tohailfinger2010-07-081-1/+1
| | | | | | | | | | | | extract_programmer_param. Programmer parameters can no longer be separated with a colon, they have to be separated with a comma. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Various places in the flashrom source feature custom parameterhailfinger2010-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | extraction from programmer_param. This led to wildly differing syntax for programmer parameters, and it also voids pretty much every assumption you could make about programmer_param. The latter is a problem for libflashrom. Use extract_param everywhere, clean up related code and make it more foolproof. Add two instances of exit(1) where we have no option to return an error. Remove six instances of exit(1) where returning an error was possible. WARNING: This changes programmer parameter syntax for a few programmers! Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* If a programmer has untested or non-working write/erase code, buthailfinger2010-07-031-0/+1
| | | | | | | | | | | | | probing/reading works, it makes sense to protect the user against write/erase accidents. This feature will be used by the Nvidia MCP SPI code, and it also might make sense for the gfxnvidia driver which has non-working write/erase. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1069 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Kill global variables, constants and functions if local scope suffices.hailfinger2010-07-031-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | Constify variables where possible. Initialize programmer-related variables explicitly in programmer_init to allow running programmer_init from a clean state after programmer_shutdown. Prohibit registering programmer shutdown functions before init or after shutdown. Kill some dead code. Rename global variables with namespace-polluting names. Use a previously unused locking helper function in sst49lfxxxc.c. This is needed for libflashrom. Effects on the binary size of flashrom are minimal (300 bytes shrinkage), but the data section shrinks by 4384 bytes, and that's a good thing if flashrom is operating in constrained envionments. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add SPI chip read support to the dummy flasher. This allows using thehailfinger2010-06-201-0/+1
| | | | | | | | | | dummy flasher for SPI read debugging. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* National Semiconductor DP83815/DP83816 and DP83820 NIC programmerhailfinger2010-06-071-1/+12
| | | | | | | | | | | | support. Some instability remains, but that may be due to hardware problems in the specific card (Netgear FA311) used for testing. Signed-off-by: Andrew Morgan <ziltro@ziltro.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* board_enable.c: Remove useless 'name' parameter.uwe2010-06-071-2/+2
| | | | | | | | | | | | | | Every board-enable function is passed a 'const char *name' (board name) which is totally useless as the board name was already printed by flashrom at that point. Also, 95% or so of the board-enables don't use the parameter anyway. So, drop it. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1037 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix wiki board enable parameter printing. The logic was incorrect in onehailfinger2010-06-071-6/+0
| | | | | | | | | | | place which had && instead of ||. Move the board info #define B to the file where it is used. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* gcc and clang can check format strings of printf-like functions. Sincehailfinger2010-06-041-1/+2
| | | | | | | | | | | | | we don't support any other compilers right now, enable that extension unconditionally. Fix the bugs found by format string checking. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1032 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* The internal programmer needs correct information about flash_base andhailfinger2010-06-041-0/+3
| | | | | | | | | | | | | | chip window top/bottom alignment on non-x86 before it can be used. Abort any internal programmer action for now until the code is fixed. Add the concept of a processor enable for systems where flashing is impacted by processor settings or processor model. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix fallout from r1021 which caused compile failures if only the dummyhailfinger2010-06-031-4/+1
| | | | | | | | | | programmer was selected. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Merge print.c and print_wiki.c board/URL tables.uwe2010-06-011-4/+14
| | | | | | | | | | | | Also, merge the tables in the output, i.e. there's only one table which contains both known-good and known-bad/untested boards. Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* So far, we have up to 4 different names for the same thing (ignoringhailfinger2010-05-311-30/+30
| | | | | | | | | | | | | | | | | | | | | | capitalization): CONFIG_FT2232SPI (makefile config option) FT2232_SPI_SUPPORT (#define) ft2232spi (programmer name) ft2232_spi.c (programmer file) Use CONFIG_* with underscores for makefile config options and #defines and kill the useless _SUPPORT idiom. Use lowercase names with underscores for programmer names and programmer files. With this, you can run "grep -i ft2232_spi" and find everything related to the ft2232_spi driver. Same applies to all other programmers. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove unneeded #include statements completely.hailfinger2010-05-301-3/+4
| | | | | | | | | | | | | | | | unistd.h was only used to get a definition of NULL in all files. Add our own NULL #define and remove unistd.h from flash.h stdio.h has no place in flash.h, it should be included only in files which really need it. Add #include statements in individual .c files where needed. Replace a few printf with msg_* to eliminate the need for stdio.h. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* ICH SPI can enforce address restrictions for all accesses which take anhailfinger2010-05-281-0/+2
| | | | | | | | | | | | | | | address (well, it could if the chipset implementation was not broken). Since exploiting the broken implementation is harder than conforming to the address restrictions wherever possible, conform to the address restrictions instead. This patch eliminates a lot of transaction errors people were seeing on chip probe. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Handle the following architectures in generic flashrom code:hailfinger2010-05-261-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian) No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them. Compilation should work on all architectures listed above for all drivers except nic3com and nicrealtek which require PCI Port IO which is x86-only for now. To compile without nic3com and nicrealtek, run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no Thanks to Misha Manulis for testing early versions of this patch on PowerPC (big endian) with the satasii programmer. Thanks to Segher Boessenkool for design review and for helping out with compiler tricks and pointing out that we need eieio on PowerPC. Thanks to Vladimir Serbinenko for compile testing on MIPS (little endian) and PowerPC (big endian) and for runtime testing on MIPS (little endian). Thanks to David Daney for compile testing on MIPS (big endian). Thanks to Uwe Hermann for compile and runtime testing on x86_64. DO NOT RUN FLASHROM ON NON-X86 AFTER APPLYING THIS PATCH! This patch only provides the infrastructure, but does not convert any drivers, so flashrom will compile, but it won't do the right thing on non-x86 platforms. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Misha Manulis <misha@manulis.com> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Segher Boessenkool <segher@kernel.crashing.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support for Realtek RTL8139 network card flashing.hailfinger2010-05-211-1/+17
| | | | | | | | Signed-off-by: Joerg Fischer <turboj@gmx.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix assorted documentation, frontend and printing bugs.hailfinger2010-05-151-0/+1
| | | | | | | | | | | Change the command line interface to make file names positional. Add more sanity checks to the command line parser. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* --force may have been a good idea back when only developers were usinghailfinger2010-04-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flashrom, but over the last few months we've seen too many people who incorrectly believed that --force would solve anything. One of the problems is that --force had multiple meanings: - Force chip read by faking probe success. - Force chip access even if the chip is bigger than max decode size for the flash bus. - Force erase even if erase is known bad. - Force write even if write is known bad. - Force writing even if cbtable tells us that this is the wrong image for this board. This patch cleans up --force usage: - Remove any suggestions to use --force for probe/read from flashrom output. - Don't talk about "success" or "Found chip" if the chip is forced. - Add a new internal programmer parameter boardmismatch=force. This overrides any mismatch detection from cbtable/image comparisons. - Add a new internal programmer parameter laptop=force_I_want_a_brick. - Adjust the documentation for --force. - Clean up the man page a bit whereever it talks about --force or laptops. Additional changes in this patch: - Add warnings about laptops to the documentation. - Abort if a laptop is detected. Can be overridden with the programmer parameter mentioned above. - Add "Portable" to the list of DMI strings indicating laptops. - Check if a chip specified with -c is known to flashrom. - Programmer parameter reliability and consistency fixes. - More paranoid self-checks. - Improve documentation. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Intel 28F004/28F400 supportmkarcher2010-04-031-1/+1
| | | | | | | | | | | | | | | | | Remove blockwise write for i82802ab chips. It will be reintroduced in post-0.9.2 in a generic way. This is needed to fix FWH-like chips with non-uniform sectors. These are: Intel 28F001 Sharp LHF00L04 ST M50FW002 ST M50LPW116 Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Multibyte SPI write for the Bus Pirate.hailfinger2010-03-221-0/+1
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Write granularity is chip specific. The following writehailfinger2010-03-081-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | granularities exist according to my datasheet survey: - 1 bit. Each bit can be cleared individually. - 1 byte. A byte can be written once. Further writes to an already written byte cause the contents to be either undefined or to stay unchanged. - 128 bytes. If less than 128 bytes are written, the rest will be erased. Each write to a 128-byte region will trigger an automatic erase before anything is written. Very uncommon behaviour. - 256 bytes. If less than 256 bytes are written, the contents of the unwritten bytes are undefined. Note that chips with default 256-byte writes, which keep the original contents for unwritten bytes, have a granularity of 1 byte. Handle 1-bit, 1-byte and 256-byte write granularity. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Implement tested/untested status for board enablesmkarcher2010-02-281-0/+2
| | | | | | | | | | | | | | | The message printing code greatly exceed the 80 character limit. I can reformat it on request to obey the limit. Intended behaviour: on untested boards an explanation of that status is printed and the board enable code is not run, unless the option "boardenable=force" has been passed to the internal programmer. Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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