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* Random whitespace and coding-style fixes.uwe2011-07-281-107/+101
| | | | | | | | | | | | | | Also, indentation fixes, e.g. due to conversion to msg_*, use ARRAY_SIZE where possible, wrap overly long line, etc. Compile-tested. There should be no functional changes. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rename CHIP_BUSTYPE_FOO to BUS_FOO.hailfinger2011-07-271-5/+5
| | | | | | | | | | It's shorter to type, and we have less problems with the 80 column limit. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* add a bunch of new/tested stuff and various small changes 6stefanct2011-07-261-1/+1
| | | | | | | | | | | | | | | | | - add J-7BXAN to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-July/007397.html - fix urls, typos, whitespace etc. - fix counting of supported chips in the wiki output Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> the last one is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> everything else is Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix output of erase_and_write_flash and surroundingsstefanct2011-07-261-13/+16
| | | | | | | | | | | | see http://www.flashrom.org/pipermail/flashrom/2011-July/007220.html for a discussion about the details. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* add a bunch of new/tested stuff and various small changes 5stefanct2011-07-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - mark EN25F80 as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007329.html - mark W25Q16 as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007151.html - mark W39V040A as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007161.html - mark Pm25LV040 as fully tested reported by TL1 on IRC - mark W49F002U/N as fully tested http://paste.flashrom.org/view.php?id=733g - mark W39V080FA as fully tested http://www.flashrom.org/pipermail/flashrom/2011-July/007225.html - add ASUS P4S533-X to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-July/007200.html - add ASUS M4A785TD-V EVO to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-July/007329.html - add GA-945PL-S3P (rev. 6.6) to the list of supported boards reported by TL1 on IRC - add MS-7142 (K8MM-V) to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-July/007161.html - add MS-7369 (K9N Neo V2) to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-July/007181.html - add X7DBT-INF to the list of supported boards http://www.flashrom.org/pipermail/flashrom/2011-July/007225.html - mark SiS 645DX chipset enable as OK http://www.flashrom.org/pipermail/flashrom/2011-July/007200.html - mark SiS 651 chipset enable as OK http://paste.flashrom.org/view.php?id=733 - move intel_ich_gpio34_raise to the correct line(s) - change the output of unlock_w39_fwh_block from 0x%x to 0x%08x - fix output for untested chipset enables (missing space) - reorder the board enable in print.c entry for GA-8SIMLH added in r1385. - minor other fixes - fix output for multiple found flash chips by adding quotes and commas - similarly fix output of "Found/Assuming" chips Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> the last two points are Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> everything else is Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix out-of-bounds access if all erase functions fail.hailfinger2011-07-211-6/+8
| | | | | | | | | | | | | Fix detection of unchanged chip contents on erase failure. Return error if no usable erase functions exist. Thanks to Stefan Tauner for spotting the last problem. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* fix unchecked malloc calls and casts of malloc return valuesstefanct2011-07-121-3/+15
| | | | | | | | | | | | in the long term the exit calls should be replaced by returns. until then this is the correct way to handle failures. the casts are not needed (in C) and we don't cast malloc return values anywhere else. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Kill unused "log" argument of count_usable_erasers().stefanct2011-07-041-5/+4
| | | | | | | Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* add count_usable_erasers which returns the number of well-defined erasers ↵stefanct2011-07-011-12/+22
| | | | | | | | | | | | | for a chip It solves one FIXME and consequentially allows to remove a later check right now, and is used in the upcoming SFDP patch. Adds a forward declaration of check_block_eraser. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* fix memleaks due to incorrect usage of flashbuses_to_textstefanct2011-06-261-3/+4
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* add a success indicator to the "Reading old flash chip contents..." messagestefanct2011-06-261-1/+3
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* constify (a few) parameters in flashrom.c where possiblestefanct2011-06-261-8/+8
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Erase functions are no longer called from chip drivers and thus theirhailfinger2011-06-261-0/+4
| | | | | | | | | | | | | internal erase verification can be moved to generic code. This also makes it easier to skip the verify step if desired and to differentiate between failed command submission and failed erase verification. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* fix probe_flash to report new values set by probing functionsstefanct2011-06-251-2/+2
| | | | | | | | | | This is needed if the probing function changes its fill_flash parameter like in the pattern used to support Intel Hardware Sequencing and SFDP. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Do not display skipped probe messsages in verbose mode.hailfinger2011-06-171-10/+11
| | | | | | | | | | They are still visible in spew mode (-VV). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use shutdown callback mechanism to shutdown programmersdhendrix2011-06-141-22/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch attempts to resolve some programmer shutdown ordering issues by having the programmer init functions register shutdown callbacks explicitly wherever it makes most sense. Before, assumptions were made that could lead to the internal programmer's state changing before the external programmer could be shut down properly. Now, each programmer cleans up after itself and (hopefully) performs each operation in the correct order. As a side-effect, this patch gives us a better usage model for reverse operations such as rpci_* and rmmio_*. In the long-run, this should make reversing the initialization process easier to understand, less tedious, and less error-prone. In short, this patch does the following: - Registers a shutdown callback during initialization for each programmer. - Kills the .shutdown function pointer from programmer_entry struct. Also, make most shutdown functions static. - Adds a few minor clean-ups and corrections (e.g. missing physunmap() calls). TODO: Remove forward declaration of serprog_shutdown() (added to simplify diff) Signed-off-by: David Hendricks <dhendrix@google.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1338 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* small fixesstefanct2011-05-281-3/+3
| | | | | | | | | | | - missing spaces in code and output - improved documentation/naming/output - missing line breaks in spi probing functions Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* eliminate magic numbers indicating maximum column sizes in ↵stefanct2011-05-261-0/+28
| | | | | | | | | | | | | print_supported_chipsets and print_supported_boards_helper without this the magic numbers need to be kept in sync with the maximum length of the strings printed in the corresponding column. if not, an overflow and a nasty ' '-storm occur on executing flashrom -L. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1318 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* whitespace, documentation and other small stuffstefanct2011-05-191-2/+2
| | | | | | | | | | | | | | | this patch combines three previously posted patches in a revised form. one is even stolen from Stefan Reinauer (remove umlauts from man page). Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Signed-off-by: Stefan Reinauer <reinauer@google.com> some parts are Acked-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006@gmx.net> the rest is Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1317 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove filename parameter from chip_safety_check()stefanct2011-05-181-2/+2
| | | | | | | Signed-off-by: David Hendricks <dhendrix@google.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* kill central list of SPI programmersmkarcher2011-05-111-8/+1
| | | | | | | | | | | | | | | | | | Remove the array spi_programmer, replace it by dynamic registration instead. Also initially start with no busses supported, and switch to the default non-SPI only for the internal programmer. Also this patch changes the initialization for the buses_supported variable from "everything-except-SPI" to "nothing". All programmers have to set the bus type on their own, and this enables register_spi_programmer to just add the SPI both for on-board SPI interfaces (where the internal programmer already detected the other bus types), as well as for external programmers (where we have the default "none"). Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Intel NIC with parallel flash support.hailfinger2011-05-081-1/+23
| | | | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Anton Kochkov <anton.kochkov@gmail.com> Acked-by: Anton Kochkov <anton.kochkov@gmail.com> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Constify flashchips array.hailfinger2011-05-041-15/+26
| | | | | | | | | | This moves 99.5% of the .data section to .rodata (which ends up in .text). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for more than one Super I/O or EC per machine.hailfinger2011-04-271-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | flashrom currently only supports exactly one Super I/O or Embedded Controller, and this means quite a few notebooks and a small subset of desktop/server boards cannot be handled reliably and easily. Allow detection and initialization of up to 3 Super I/O and/or EC chips. WARNING! If a Super I/O or EC responds on multiple ports (0x2e and 0x4e), the code will do the wrong thing (namely, initialize the hardware twice). I have no idea if we should handle such situations, and whether we should ignore the second chip with identical ID or not. Initializing the hardware twice for the IT87* family is _not_ a problem, but I don't know how well IT85* can handle it (and whether IT85* would listen at more than one port anyway). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Thanks to Thomas Schneider for testing on a board with ITE IT87* SPI. Test report (success) is here: http://paste.flashrom.org/view.php?id=379 Thanks to David Hendricks for testing on a Google Cr-48 laptop with ITE IT85* EC SPI. Test report (success) is here: http://www.flashrom.org/pipermail/flashrom/2011-April/006275.html Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix compilation if CONFIG_INTERNAL=no.hailfinger2011-03-081-3/+4
| | | | | | | | | | | | Fix compilation if everything except CONFIG_SATAMV is no. Do not compile in PCI support for wiki printing if no PCI devices are supported. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Simplify pcidev_init by killing the vendorid parameter which was prettyhailfinger2011-03-071-17/+2
| | | | | | | | | | | | | | | useless anyway since it was present in the pcidevs parameter as well. This also allows us to handle multiple programmers with different vendor IDs in the same driver. Fix compilation of flashrom with only the nicrealtek driver. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support for Angelbird Wings PCIe SSD (solid-state drive).hailfinger2011-02-041-1/+23
| | | | | | | | | | | | | | | | It uses a Marvell 88SX7042 SATA controller internally which has access to a separate flash chip hosting the option ROM. Thanks to Angelbird Ltd for sponsoring development of this driver! I expect the code to work for that SATA controller even if it is not part of the Angelbird SSD. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Don't print the local memory flash chip address on programmers that don'tstepan2011-01-191-2/+9
| | | | | | | | | | | | | actually map the flash chip into local memory (like the dediprog) because the value does not make sense there. This version was reworked / rewritten by Mathias Krause to have less "impact" Signed-off-by: Stefan Reinauer <reinauer@google.com> Acked-by: Mathias Krause <mathias.krause@secunet.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch reduces the stack usage by declaring 'const' stack variableskrause2011-01-171-1/+1
| | | | | | | | | | | | | | as 'static const' so they end up in the .rodata section instead of being copied from there to the stack for every invocation of the corresponding function. As a plus we end up in having a smaller binary as the "copy from .rodata to stack" code isn't emitted by the compiler any more (roughly -100 bytes). Signed-off-by: Mathias Krause <mathias.krause@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Simplify get_next_write in the partial write code.hailfinger2010-12-061-3/+1
| | | | | | | | | | Suggested by Michael Karcher. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Clean up erase function checking.hailfinger2010-12-051-24/+41
| | | | | | | | | | Update a few comments and messages to improve readability. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Open Graphics Project development card, OGD1, as ahailfinger2010-12-031-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI flash programmer. The project is in the the process of designing and making a complete, open source, graphics card. More info at http://wiki.opengraphics.org. The first development card is a PCI add in card containing a couple of FPGAs and a couple of serial flash chips (amongst other things). The FPGAs are called XP10 and S3 (their part numbers). The XP10 contains its own flash and does not need to be programmed by flashrom - it ensures that the device can enumerate on the PCI bus without needing further configuration. The larger FPGA is the S3. This is configured from a large SPI flash (2 MBytes). The second SPI flash is used to store the VGA BIOS. It is smaller (128 KBytes). This patch adds support for programming either of the two SPI flash chips. The programmer device takes one configuration option which selects which of the two flash chips is accessed. This must be set to either "cprom" or "bprom". (The project refers to the two chips as "cprom" / "bprom", "s3" and "bios" are more readable alternatives). Add support for SST SST25VF010 (REMS). Mark SST SST25VF016B as tested for write. Signed-off-by: Mark Marshall <mark.marshall@csr.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Avoid printing the chip locks if chip detection was forced because lockhailfinger2010-12-021-2/+6
| | | | | | | | | | access may involve flash chip registers which will not be mapped. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Handle erase failure in partial write.hailfinger2010-12-021-4/+13
| | | | | | | | Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Read the to-be-verified area in one go.hailfinger2010-11-161-33/+17
| | | | | | | | | | | | | | | | | verify_range() and check_erased_range() check each page separately. While that may have seemed like a good idea back when the code was introduced, it has no benefits for any of the chips where we support write because all of them handle cross-page reads nicely. The only class of chips where this change could be a problem is chips with non power of two sector sizes which have gaps in the address space. We simply require their read functions to provide gap-free results and leave it at that. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-By: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Revert PCI config space writes on shutdown.hailfinger2010-11-101-1/+1
| | | | | | | | | | | | | | | | This means all chipset enables etc. will be undone on shutdown. Reversible PCI config space writes now use rpci_write_*(). PCI config space writes which are one-shot (e.g. communication via config space) should continue to use the permanent pci_write_* variants. Extend the number of available register_shutdown slots to 32. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Support setting the Dediprog SF100 SPI voltage.hailfinger2010-11-091-0/+7
| | | | | | | | | | | | Add a generic voltage parameter parser. Move tolower_string() from dummyflasher.c to flashrom.c to make it available everywhere. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Avoid two memory leaks in doit() which were unproblematic for flashromhailfinger2010-11-051-81/+63
| | | | | | | | | | | | | | | | | | because flashrom terminates after finishing doit(). Rename oldcontents to curconents in erase_and_write_block_helper(). Unify the code for all granularities in get_next_write(). Return write length from get_next_write() instead of filling it as referenced parameter. Thanks to Michael Karcher for pointing out the first two issues. Thanks to David Hendricks for pointing out the third issue and suggesting a way to unify that code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch makes flashrom use real partial writes. If you write an imagehailfinger2010-11-041-40/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | full of 0xff, flashrom will erase and detect that no write is needed. If you write an image which differs only in some parts from the current flash contents, flashrom will detect that and not touch unchanged areas. Fix a long-standing bug in need_erase() for 256 byte granularity as well. Nice side benefit: Detailed progress printing. S means skipped E means erased W means written Thanks to Andrew Morgan for testing countless iterations of this patch. Thanks to Richard A. Smith for testing on Dediprog SF100. Thanks to David Hendricks for the review and for creating a partial write torture test script and testing with it on Intel NM10 and AMD SB700 SPI. Thanks to Idwer Vollering for testing with Intel SPI NICs. Thanks to Rudolf Marek for testing on AMD SB710 and SiI SATA controllers. Thanks to Michael Karcher for the review. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: David Hendricks <dhendrix@google.com> Acked-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Always read the flash chip before writing. This will allow flashrom tohailfinger2010-10-191-11/+66
| | | | | | | | | | | | | | | | | | | | | | skip erase of already-erased blocks and to skip write of blocks which already have the wanted contents. Avoid emergency messages by checking if the chip contents after a failed write operation (erase/write) are unchanged. Keep the emergency messages after a failed pure erase. That part is debatable because if someone wants erase, he pretty sure doesn't care about the flash contents anymore. Please note that this introduces additional overhead of a full chip read before write. This is frowned upon by people with slow programmers. A followup patch will make this configurable. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* doit() is the monster function we split off from main() when we createdhailfinger2010-10-151-81/+100
| | | | | | | | | | | | | cli_classic() and tried to introduce some abstraction. doit() is a poster child of WTFs on an astronomic scale. Make doit() less bad by factoring out self-contained code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Switch all flash chips to partial write.hailfinger2010-10-131-1/+1
| | | | | | | | | | | | | | | | The inner write functions which handle partial write are renamed to the original name of their wrappers. The write wrappers are removed. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Tested-by: Andrew Morgan <ziltro@ziltro.com> Tested-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Idwer Vollering <vidwer@gmail.com> Tested-by: Sean Nelson <audiohacked@gmail.com> Acked-by: Sean Nelson <audiohacked@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* flashrom had an implicit erase-on-write for most flash chip andhailfinger2010-10-081-9/+17
| | | | | | | | | | | | | | | | | programmer drivers, but it was not entirely consistent. Some drivers had their own hand-rolled partial update functionality which made handling partial updates from generic code impossible. Move implicit erase out of chip drivers, and kill some dead erase functions at the same time. A full chip erase is now performed in the generic code for all flash chips on write, and after that the whole chip is written. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* A lot of messages sent to flashrom@flashrom.org just have "flashrom -V"hailfinger2010-10-081-3/+4
| | | | | | | | | | | | as the subject. Ask people to include more information in the subject line to make life easier for developers/supporters. Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* flashrom -L output did not contain a list of programmers nor were allhailfinger2010-10-061-0/+41
| | | | | | | | | | | | programmers listed. Fix it and mention at least the name of each programmer. Wiki output is unchanged, and will need separate fixups. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for building flashrom against libpayload.oxygene2010-09-301-1/+3
| | | | | | | | | | | | This doesn't include changes to the frontend which must be done separately, so this won't work out of the box. This code was tested on hardware. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add Intel Gigabit NIC SPI flashing support.uwe2010-09-031-1/+23
| | | | | | | | | | | | | | | | | | | | | | Tested on a 82541PI (0x8086, 0x107c) using 32-bit hardware. The last line in nicintel_request_spibus() could be changed so that FL_BUSY is used instead. Shortened sample log: [...] Found "Intel 82541PI Gigabit Ethernet Controller" (8086:107c, BDF 01:03.0). Found chip "ST M25P10.RES" (128 KB, SPI) at physical address 0xfffe0000. Multiple flash chips were detected: M25P05.RES M25P10.RES Please specify which chip to use with the -c <chipname> option. [...] Signed-off-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Various cosmetic and coding-style fixes (trivial).uwe2010-08-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | - Fix incorrect whitespace, indentation, and coding style in some places. - Drop '/**' Doxygen comments, we don't use Doxygen. Even if we would use it, the comments are useless as we don't have any Doxygen markup in there. - Use consistent vendor name spelling as per current website (NVIDIA, abit, GIGABYTE). - Use consistent / common format for "Suited for:" lines in board_enable.c. - Add some missing 'void's in functions taking no arguments. - Add missing fullstops in sentences, remove them from non-sentences (lists). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Split off programmer.h from flash.h.hailfinger2010-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | Programmer specific functions are of absolutely no interest to any file except those dealing with programmer specific actions (special SPI commands and the generic core). The new header structure is as follows (and yes, improvements are possible): flashchips.h flash chip IDs chipdrivers.h chip-specific read/write/... functions flash.h common header for all stuff that doesn't fit elsewhere hwaccess.h hardware access functions programmer.h programmer specific functions coreboot_tables.h header from coreboot, internal programmer only spi.h SPI command definitions Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for RayeR SPIPGM hardware as described inhailfinger2010-07-211-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://rayer.ic.cz/elektro/spipgm.htm To use the RayeR driver, run flashrom -p rayer_spi -V Known bugs/limitations: - Won't compile/work on non-x86 architectures. - Will always use direct port I/O access. Log follows: flashrom v0.9.2-r1039 on MS-DOS 7 (i686), built with libpci 3.1.5, GCC 4.3.2, little endian Calibrating delay loop... OK. Initializing rayer_bitbang_spi programmer Using port 0x378 as I/O base for parallel port access. ... Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 ... Found chip "Macronix MX25L1605" (2048 KB, SPI) at physical address 0xffe00000. ... No operations were specified. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Martin Rehak <rayer@seznam.cz> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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