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ichspi.c
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Age
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*
There are various reasons why a SPI command can fail. Among others, I
hailfinger
2009-05-13
1
-1
/
+1
*
Trim default ICH SPI delay from 1000 to 10 microseconds. Since many
hailfinger
2009-05-09
1
-4
/
+4
*
Chips like the SST SST25VF080B can only handle single byte writes
hailfinger
2009-05-09
1
-1
/
+1
*
Original v2 revision: 4117
uwe
2009-04-15
1
-7
/
+5
*
Original v2 revision: 3918
stuge
2009-01-26
1
-1
/
+0
*
Original v2 revision: 3862
stuge
2009-01-15
1
-0
/
+1
*
Original v2 revision: 3814
stuge
2008-12-15
1
-27
/
+30
*
Original v2 revision: 3805
stepan
2008-12-08
1
-0
/
+134
*
Original v2 revision: 3758
hailfinger
2008-11-18
1
-9
/
+5
*
Original v2 revision: 3722
hailfinger
2008-11-03
1
-16
/
+5
*
Original v2 revision: 3721
stepan
2008-11-02
1
-15
/
+45
*
Original v2 revision: 3669
uwe
2008-10-18
1
-12
/
+12
*
Original v2 revision: 3417
stuge
2008-07-07
1
-3
/
+3
*
Original v2 revision: 3401
stepan
2008-06-30
1
-53
/
+54
*
Original v2 revision: 3398
ruik
2008-06-30
1
-26
/
+44
*
Original v2 revision: 3397
hailfinger
2008-06-29
1
-1
/
+2
*
Original v2 revision: 3395
stuge
2008-06-29
1
-1
/
+1
*
Original v2 revision: 3393
stepan
2008-06-27
1
-41
/
+211
*
Original v2 revision: 3392
stepan
2008-06-27
1
-48
/
+40
*
Original v2 revision: 3325
hailfinger
2008-05-16
1
-0
/
+468