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enable. We could run it after chipset enable, but it definitely has to
happen before board enable because the board enable usually accesses the
SuperI/O.
With this patch, it is possible to add a struct superio to the board
enable table for more accurate matching in case subsystem IDs are
ambiguous.
This patch focuses on the generic infrastructure aspect and on support
for IT8712F/IT8716F.
Thanks go to Adrian Glaubitz and Ward Vandewege for testing.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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disabled.
Make various pieces of code conditional on support for internal
programming. Code shared between PCI device programmers and onboard
programming is now conditional as well.
It is now possible to build only with dummy support:
make CONFIG_INTERNAL=no CONFIG_NIC3COM=no CONFIG_SATASII=no
CONFIG_DRKAISER=no CONFIG_SERPROG=no CONFIG_FT2232SPI=no
This allows building for a specific use case only, and it also
facilitates porting to a new architecture because it is possible to
focus on highlevel code only.
Note: Either internal or dummy programmer needs to be compiled in due to
the current behaviour of always picking a default programmer if -p is
not specified. Picking an arbitrary external programmer as default
wouldn't make sense.
Build and runtime tested in all 1024 possible build combinations. The
only failures are by design as mentioned above.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Sean Nelson <audiohacked@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The two existing SiS chipset enables (compared to the 28 in this patch)
were refactored, and one of them was fixed.
A function to match PCI vendor/class combinations was added to generic
code.
Tested on the "Elitegroup K7S5A". Results are somewhat unexpected (some
PCI settings seem to be inaccessible, but it still works).
This is not based on any docs, but rather on detailed analysis
of existing opensource code for some of the chipsets.
Thanks to for Adrian Glaubitz testing.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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compiled in.
Example make commandline if you want only internal programmers:
make CONFIG_FT2232SPI=no CONFIG_SERPROG=no CONFIG_NIC3COM=no
CONFIG_SATASII=no CONFIG_DRKAISER=no CONFIG_DUMMY=no
Of course, all of the CONFIG_* symbols can be mixed and matched as
needed. CONFIG_FT2232SPI is special because even if it is enabled, make
will check if the headers are available and skip it otherwise.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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been a warning only.
Even a failing chipset init (maybe due to unknown chipset) could still
get us reasonable probe results or at least forced reads.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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instead of fallback functions. The dummy programmer is a "real"
programmer with possible side effects and its functions should not be
abused by other programmers. Make FT2232 and IT87 use official fallback
functions instead.
Create fallback_shutdown().
Create fallback_chip_writeb().
Convert the programmer #defines to an enum.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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abstraction.
Kill unneeded #include statements.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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once.
Add chip_{read,write}n to the external flasher infrastructure which
read/write n bytes at once.
Fix a few places where the code used memcpy/memcmp although that is
strictly impossible with external flashers.
Place a FIXME in the layout.c code because usage is not totally clear
and needs to be fixed to support external flashers.
As a nice side benefit, we get a noticeable speedup for builtin flash
reading which is now a memcpy() of the full flash area instead of a
series of single-byte reads.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Urja Rannikko <urjaman@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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handle the delay on their own if needed.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Urja Rannikko <urjaman@gmail.com>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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and special handling here (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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others didn't (and risked non-execution of side effects) and even with
volatile, some accesses looked dubious.
Since the MMIO accessor functions and the onboard flash accessor
functions are functionally identical (but have different signatures),
make the flash accessors wrappers for the MMIO accessors.
For some of the conversions, I used Coccinelle. Semantic patch follows:
@@
typedef uint8_t;
expression a;
volatile uint8_t *b;
@@
- b[a]
+ *(b + a)
@@
expression a;
volatile uint8_t *b;
@@
- *(b) |= (a);
+ *(b) = *(b) | (a);
@@
expression a;
volatile uint8_t *b;
@@
- *(b) = (a);
+ mmio_writeb(a, b);
@@
volatile uint8_t *b;
@@
- *(b)
+ mmio_readb(b)
@@
type T;
T b;
@@
(
mmio_readb
|
mmio_writeb
)
(...,
- (T)
- (b)
+ b
)
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Uwe tested read, write, erase with this patch on a random board to make
sure nothing breaks.
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Build-tested on 32bit x86.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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chips in external flashers, they are not accessed via pointers at all.
Benefits:
This allows us to differentiate between volatile machine memory accesses
and flash chip accesses.
It also enforces usage of chip_{read,write}[bwl] to access flash chips,
so nobody will unintentionally use pointers to access chips anymore.
Some unneeded casts are removed as well.
Grepping for chip operations and machine memory operations doesn't yield
any false positives anymore.
Compile tested on 32 bit and 64 bit Linux.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@519 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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flasher infrastructure. The emulation works by splitting 32 bit accesses
into 16 bit accesses and 16 bit accesses into to 8 bit accesses.
That way, external flashers can mix and match the amount of emulation
they need.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@512 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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which all programmers can use, add missing close() call (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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notation, in case there are multiple NICs in one system.
Usage: flashrom -p nic3com=bb:ss.f
Signed-off-by: Christian Ruppert <spooky85@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@510 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- Read/write accesses through function pointers
- Command line parameter for internal/external flasher
- Board and chipset setup moved to internal init function
- Shutdown stuff moved to internal shutdown function
As a side benefit, this will allow us to undo chipset write enable
during shutdown.
Tested by Uwe on real hardware.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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