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* serprog: allow to omit specifying a baud rate.stefanct2016-01-041-3/+1
| | | | | | | | | | | On USB-based serial connections (VCP) the requested baud rate usually does not matter (much). Remove the arbitrary restriction and use whatever default values the OS/hardware provides. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Urja Rannikko <urjaman@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* serprog: Fix FWH/LPC by implementing serprog_map.stefanct2015-06-291-0/+1
| | | | | | | | | | | | | The serprog protocol does only transmit 24 bit-wide address and ignores the top 8 bit. This is fine as long as the underlying hardware ignores the latter anyway (which is the case for parallel chips that even lack the respective pins). FWH/LPC chips, however, operate on a full 32-bit (LPC) or 28-bit (FWH) address space and would fail with the fallback mapping to NULL. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1895 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the Microchip PICkit2 as an SPI programmer.stefanct2015-02-081-0/+11
| | | | | | | | | | | | | | | This patch was inspired by the code in AVRDude (open source Atmel AVR programmer) to support the PICkit2 written by Doug Brown [1]. The Dediprog code in flashrom was used as the template for this code with some reference to the ft2232 code as well. [1] - https://github.com/steve-m/avrdude/blob/master/pickit2.c Signed-off-by: Justin Chevrier <jchevrier@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 22.stefanct2015-02-081-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - AOpen UK79G-1394 (used in EZ18 barebones) Reported by Lawrence Gough - ASUS M4N78 SE Reported by Dima Veselov - ASUS P5LD2-VM Mark board enable as tested (reported by Dima Veselov) - GIGABYTE GA-970A-UD3P (rev. 2.0) Reported by trucmar on IRC - GIGABYTE GA-990FXA-UD3 (rev. 4.0) Reported by ROKO__ on IRC - GIGABYTE GA-H77-DS3H (rev. 1.1) Reported by Evgeniy Edigarev - GIGABYTE GA-P55-USB3 (rev. 2.0) Reported by Måns Thörnqvist - MSI MS-7817 (H81M-E33) Reported by Igor Kolker Chipsets: - Marked Intel Bay Trail (0x0f1c) as tested OK Reported by Antonio Ospite - Refine Intel IDs * Add IDs for Braswell * Add IDs for 9 Series PCHs (e.g. H97, Z97) * Rename Wellsburg devices slightly Flash chips: - Atmel AT25DF041A to PREW (+PREW) Reported by Tai-hwa Liang - Atmel AT26DF161 to PREW (+EW) Reported by Steve Shenton - Atmel AT45DB011D to PREW (+PREW) Reported by The Raven - Atmel AT45DB642D to PREW (+PREW) Reported by Mahesh Mokal - Eon EN25F32 to PREW (+PREW) Reported by Arman Khodabande - Eon EN25F40 to PREW (+REW) Reported by Jerrad Pierce - Eon EN25QH16 to PREW (+EW) Reported by Ben Johnson - GigaDevice GD25Q20(B) to PREW (+PREW) Reported by Gilles Aurejac - Macronix MX25U6435E/F to PR (+PR) Reported by Matt Taggart - PMC Pm25LV512(A) to PREW (+PREW) Reported by The Raven - SST SST39VF020 to PREW (+PREW) Reported by Urja Rannikko - Winbond W25Q40.V to PREW (+EW) Reported by Torben Nielsen - Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E). - Add MX25L6465E variant. - There was never a MX25L12805 AFAICT. - Split MX25L12805 from models with the same ID but an additional 32 kB eraser: MX25L12835F/MX25L12845E/MX25L12865E. - Add a bunch of ST parallel NOR flash chip IDs. Miscellaneous: - Whitelist ThinkPad X200. - Constify master parameter of register_master(). - Remove FEATURE_BYTEWRITES because it was never used at all. - Refine hwseq messages and make them less prominent. - Fix the yet unused PRIxCHIPADDR format string thingy. - Fix copy&paste error in spi_prettyprint_status_register_bp(). Spotted by Pablo Cases. - Add an additional SMBus controller revision to identify another Yangtze model. Thanks to Dan Christensen for reporting this issue. - dediprog: add missing include for stdlib.h. This fixes (at least) building on FreeBSD and DragonflyBSD with gcc. - Remove references to struct pci_filter from programmer.h. It is only needed in internal.c where it has a complete type. Having it in programmer.h provokes a warning by some old versions of gcc. - Tiny other stuff. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unify target OS and CPU architecture checks.stefanct2015-01-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | We do CPU architecture checks once for the makefile in arch.h and once for HW access abstraction in hwaccess.c. This patch unifies related files so that they can share the checks to improve maintainability and reduce the chance of inconsistencies. Furthermore, it refines some of the definitions, which - adds "support" for AARCH64 and PPC64, - adds big-endian handling on arm as well as LE handling on PPC64, - fixes compilation of internal.c on AARCH64 and PPC64. Additionally, this patch continues to unify all OS checks in flashrom by adding a new helper macro IS_WINDOWS. The old header file for architecture checking is renamed to platform.h to reflect its broader scope and all new macros are add in there. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the MSTAR I2C ISP protocol.stefanct2014-12-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Basically, among other chips, MSTAR manufactures SoCs that equip TV sets and computer screens, and it seems that all of their products use the same in-system programming protocol. Basically, they use the DDC channel of VGA or DVI connectors, which is actually an I2C bus, to encapsulate SPI frames (the flash chip is connected to the SoC through an SPI bus). I wrote this patch since the screen I bought had a software bug, and the manufacturer only released a new firmware binary, but no tool or instructions on flashing it. More details can be found here: http://boeglin.org/blog/index.php?entry=Flashing-a-BenQ-Z-series-for-free(dom) I only read code from Linux kernel archives published by Acer to figure out the protocol (for a touchscreen controller and an NFC chip, both by MSTAR, that share the same ISP protocol), so I don't think there are any legal problems with it. Compilation is currently disabled by default in the Makefile. If in doubt, additional Makefile bugs were added by Stefan. Signed-off-by: Alexandre Boeglin <alex@boeglin.org> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Intel Wildcat Point PCH.stefanct2014-08-201-0/+1
| | | | | | | | | | | The Wildcat Point PCH can be paired with Broadwell or Haswell. This patch was essentially backported from ChromiumOS commit 9bd2af8. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton.stefanct2014-08-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | The core of this patch to support Bay Trail originally came from the Chromiumos flashrom repo and was modified by Sage to support the Rangeley/Avoton parts as well. Because that was not complicated enough already Stefan Tauner refactored and refined everything. Bay Trail seems to be the first Atom SoC able to support hwseq. No SPI Programming Guide could be obtained so it is handled similarly to Lynx Point which seems to be its nearest relative. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Marc Jones <marcj303@gmail.com> Tested-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Thomas Reardon <thomas_reardon@hotmail.com> Tested-by: Wen Wang <wen.wang@adiengineering.com> Acked-By: Marc Jones <marcj303@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refine handling chips that exceed maximum programmer sizes.stefanct2014-08-151-1/+1
| | | | | | | | | | | | | | | | - Change check_max_decode() to return the number of (common) busses where the flash chip exceeds the supported size of the programmer. - Refine its signature to use a flashctx pointer only. - Move CLI-related bits to cli_classic.c. - Rename check_max_decode() to count_max_decode_exceedings() to better reflect what it (now) really does. - Refine the messages printed by the caller to better integrate with the new setup, and simplify them. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refactor some CLI-relevant parts.stefanct2014-08-081-1/+0
| | | | | | | | | | | | | | | Begin to move functions that clearly belong to the (command line) user interface out of flashrom's core files like flashrom.c. - Refine messages within check_chip_supported(), rename it to print_chip_support_status() and move it to newly created cli_common.c. - Move flashbuses_to_text() to cli_common.c as well. - Move global verbosity variables to cli_output.c. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add new programmer for SPI EEPROMs attached to Intel 82580 NICs.stefanct2014-07-281-0/+9
| | | | | | | | | | | | | | | | This patch lets you read and write the EEPROM on 82580-based gigabit NIC cards. So far it has been tested on copper NICs only, but other variants employing this controller should work too. It is a nice substitution for the official eeupdate tool. Speed is quite decent: less than 4 seconds for erases or writes of 32 kB. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rename programmer registration functionshailfinger2014-07-191-16/+16
| | | | | | | | | | | | | register_programmer suggests that we register a programmer. However, that function registers a master for a given bus type, and a programmer may support multiple masters (e.g. SPI, FWH). Rename a few other functions to be more consistent. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add selfcheck_board_enables().stefanct2014-06-121-0/+1
| | | | | | | | | | | | Check for NULL termination of the array, that each board has the two main PCI ID sets defined, that coreboot vendor and model fields are either both set or unset, and that at least either an enable function or a max decode size is available. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move global io_base_addr into compilation units.stefanct2014-06-011-2/+1
| | | | | | | Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add IT8212F as programmer.stefanct2014-06-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | This PCI PATA controller can use 3V parallel flash up to 128 kB. My card was identified as: PCI 1283:8212, subsystem 1283:0001. and labelled as: Innovision Multimedia LTD. EIO ATA133 RAID (DM-8401 Ver A) This particular card did not require setting of any GPIO signals to enable flash writing. My card has Pm39LV512 in PLCC32 package without socket. Rebased by Stefan (automatic cleanup, some PCI changes, changed enable bit handling). Committed with test state NT because the rebased version was not tested on real hardware (yet). Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add VIA VT6421A LPC programmer driver.stefanct2014-06-011-0/+10
| | | | | | | | | | | | | | | Due to the mysterious address handling of this chip the user can specify a base address with the offset parameter, e.g.: flashrom -p atavia:offset=0xFFF00000 Thanks to Idwer Vollering for his iterative testing of this code, as well as to Martijn Bastiaan who did the last tests before merging. Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* sbxxx: Add support for new AMD SPI controller.stefanct2014-05-161-0/+1
| | | | | | | | | | | | | | This patch adds support for the "SPI 100" SPI engine in Yangtze FCHs (found in Kabini and Temash). Tested reading/writing on ASRock IMB-A180 and PC Engines' APU board. Signed-off-by: Wei Hu <wei@aristanetworks.com> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add 'const' keyword to chip write and other function prototypes.stefanct2014-05-091-9/+9
| | | | | | | | | | Inspired by and mostly based on a patch Signed-off-by: Mark Marshall <mark.marshall@omicron.at> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make delay values unsigned.stefanct2014-05-021-5/+5
| | | | | | | | | | | | | | | There is no reason for negative delays in our use cases: - We don't need it (to work around any quirks). - sleep() (POSIX) uses an unsigned argument. - usleep() (POSIX) uses an unsigned argument. - Sleep() (Windows) uses an unsigned argument. Change all callees as well (without any complications). Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Clean up physmap, fix unaligned mapping problemshailfinger2014-03-051-1/+2
| | | | | | | | | | | | | Convert all physmaps in dmi.c to use aligned readonly maps. Convert all physmaps in cbtable.c to use unaligned readonly maps. Make physunmap() a generic architecture-independent wrapper. Add physunmap_unaligned() to complement physmap*_unaligned(). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refactor Intel Chipset Enables.stefanct2013-10-251-6/+6
| | | | | | | | | | | | | | | | | | | | | - Combine enable_flash_ich_4e() and enable_flash_ich_dc() to enable_flash_ich_fwh(). - Remove unjustified (chipset) name parameters from various enable_flash_ich* functions. - Make Poulsbo and Tunnel Creek use generic enables by refining existing functions to work with them, including everything in ichspi.c. - Refactor enable_flash_ich_fwh_decode() to be called unconditionally for all chipsets. - Add support for Intel Atom Centerton (S12x0). - Recombine ICH2/3/4/5 to CHIPSET_ICH2345 because we treat them equally anyway. - Move spibar handling out of ich_init_spi() into enable_flash_ich_spi() - Various small cleanups. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use ich_generation parameter in enable functions prior to ICH7.stefanct2013-09-141-2/+7
| | | | | | | | | | | Follow the style used from ICH7 onwards to pass ich_generation parameter to lower-level functions on older ICH chipsets too. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Remove exit call and mayfail parameter from physmap_common().stefanct2013-09-141-1/+1
| | | | | | | | | | | | | | | The only call path where exit was reached was from physmap functions. Callers of physmap() et al. which were not prepared to handle ERROR_PTR return values have been adjusted. physmap_try_ro() has been renamed to physmap_ro() and physmap_common() slightly refactored due to the now removed *FAIL parameters. Signed-off-by: Niklas Söderlund <niso@kth.se> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add an internal DMI decoder.stefanct2013-09-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we had to rely on dmidecode to decode the DMI/SMBIOS table. This patch integrates a DMI decoder into flashrom. The old behavior of calling dmidecode can be brought back by using CONFIG_INTERNAL_DMI=no. Significant portions of this patch were taken from dmidecode, hence add its authors to the copyright notice (dmidecode is also GPL2+). We do a few things differently though. First of all we do more bounds checking to prevent accessing unmapped memory. We do not support disovery via EFI (yet), but memory scanning only. We handle the chassis-type lock bit correctly which dmidecode did not for a long while. The API to the rest of flashrom remains stable, but the output changes slightly. To share as much code as possible (which actually is not much), i have added dmi_fill methods that get called in dmi_init. They are reponsible to fill the dmi_strings array and setting the is_laptop variable. After it is called, dmi_init prints all dmi_strings. Previously the strings were printed in the order they were discovered, followed by the chassis-type, which is now output earlier (in dmi_fill). Because DJGPP does not support strnlen a simple implementation was added for it. This is still only available on x86; actually it is not even compiled in for other architectures at all anymore. Signed-off-by: Sean Nelson<audiohacked@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Tested-by: Maciej Pijanka <maciej.pijanka@gmail.com> Tested-by: Idwer Vollering <vidwer@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Get rid of sp_die().stefanct2013-08-241-1/+0
| | | | | | | | | | | | | | - Add return values to sp_flush_stream(), sp_pass_writen(), sp_execute_opbuf(), sp_execute_opbuf_noflush(), sp_check_opbuf_usage(), sp_do_read_n(). - Use those return values to propagate errors instead of exiting. In some places this has to wait for core API changes (error handling for chip_readb, chip_readn, chip_write) hence comments are added instead. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce serialport_config().stefanct2013-08-231-0/+1
| | | | | | | | | | This allows to easily reconfigure a serial port as needed in the Bus Pirate speedup patch. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Automatically unmap physmap()s.stefanct2013-08-141-0/+1
| | | | | | | | | | | | Similarly to the previous PCI self-clean up patch this one allows to get rid of a huge number of programmer shutdown functions and makes introducing bugs harder. It adds a new function rphysmap() that takes care of unmapping at shutdown. Callers are changed where it makes sense. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a bunch of new/tested stuff and various small changes 19.stefanct2013-08-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASUS P8H77-V LE http://www.flashrom.org/pipermail/flashrom/2013-June/011127.html - HP Pegatron IPMEL-AE (Evans-GL6) Reported by Idwer on IRC - MSI MS-7379 (G31M) http://paste.flashrom.org/view.php?id=1726 - MSI MS-7816 (H87-G43) http://www.flashrom.org/pipermail/flashrom/2013-July/011349.html - MSI MS-9830 (IM-945GSE-A, A9830IMS) http://paste.flashrom.org/view.php?id=1730 - Supermicro X8SAX http://paste.flashrom.org/view.php?id=1717 NOT OK: - Intel D2700MUD http://paste.flashrom.org/view.php?id=1723 - Intel DQ45CB http://www.flashrom.org/pipermail/flashrom/2013-August/011369.html Chipsets: - Add PCI ID for Intel's Coleto Creek. - Mark Intel H87 (0x8c4a) as OK. http://www.flashrom.org/pipermail/flashrom/2013-July/011349.html Miscellaneous: - ichspi: Fix printing address ranges if space is divided by FPB. - Tiny other stuff. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* sbxxx: Handle active IMCs in AMD chipsets.stefanct2013-07-251-0/+3
| | | | | | | | | | | | Detect and temporarily disable the IMC while accessing the flash. Disable writes on default, but allow the user to enforce it. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: David Hendricks <dhendrix@google.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* uintptr_t-ify map_flash_region functions.stefanct2013-07-171-5/+5
| | | | | | | | | | | | | | | | | | | unsigned long is not the right type for manipulating pointer values. Since C99 there are suitable unsigned and signed types available, namely uintptr_t and intptr_t respectively. Use them in functions assigned to programmers' map_flash_region fields and their callers where applicable. This patch also changes the display width of all associated address values in physmap.c to 16/8 hex characters depending on the actual size by introducing a macro PRIxPTR_WIDTH and exploiting printf's * field width specifier. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* usleep() is not found in all versions of MinGW, use Sleep() on Windows.hailfinger2013-04-051-0/+1
| | | | | | | | | | | Handle long sleeps on non-Windows correctly. Signed-off-by: Maksim Kuleshov <mmcx@mail.ru> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce serialport_write_nonblock().stefanct2013-04-011-0/+1
| | | | | | | | | | | | | It seems useful to have a generic and platform-independent method to read and write to a serial port without blocking. This is the write part. This allows to get rid of the explicit temporary disabling of blocking I/O in serprog's sp_synchronize(). Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Replace sp_sync_read_timeout() with serialport_read_nonblock().stefanct2013-04-011-0/+1
| | | | | | | | | | | | | | | It seems useful to have a generic and platform-independent method to read and write to a serial port without blocking. This is the read part. It stores the current blocking properties before disabling blocking and restores them after reading. The timeout is implemented as previously by retrying every millisecond until the timeout is reached or enough characters are available. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add Altera USB-Blaster SPI programmer.stefanct2013-03-271-0/+12
| | | | | | | | | | | | | Adds support for the Altera USB-Blaster programming dongle in Active Serial (AS) mode. Tested on both original product and a clone dongle. Signed-off-by: James Laird <jhl@mafipulation.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Intel Lynx Point low-power and Wellsburg.stefanct2013-03-151-1/+3
| | | | | | | | | | | | | | New IDs taken from Intel's patches for the Linux kernel. Also, refine original Lynx Point naming etc. Based on the chromiumos patch Change-Id: I303a05baa80e4449e70d20adf78ebc7128b88d8e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Decouple BAR reading from pci device init, handle errors gracefully.hailfinger2013-01-051-18/+18
| | | | | | | | | | | | | | | | pcidev_init() now returns struct pci_device * instead of a BAR stored in PCI config space. This allows for real error checking instead of having exit(1) everywhere in pcidev.c. Thanks to Niklas Söderlund for coming up with the original error handling patch which was slightly modified and folded into this patch. Move the declaration of struct pci_device in programmer.h before the first user. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unify PCI init and let pcidev clean itself up.stefanct2013-01-041-0/+1
| | | | | | | | | | | | | | | | | | | Previously the internal programmer used its own code to initialize pcilib. This patch extracts the common code from the internal programmer and pcidev_init() into pcidev_init_common(). This fixes the non-existent PCI cleanup of the internal programmer and adds an additional safety by checking for an already existing PCI context. We got a nice shutdown function registration infrastructure, but did not use it very wisely. Instead we added shutdown functions to a myriad of programmers unnecessarily. In this patch we get rid of those that do only call pci_cleanup(pacc) by adding a shutdown function the pcidev.c itself that gets registered by pcidev_init(). Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Constify parameters and globals.stefanct2012-12-301-1/+1
| | | | | | | | | | | This makes some stuff const (partially to get a more convenient libflashrom interface). Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Unify usbdev_status and pcidev_status into dev_entry.stefanct2012-12-271-37/+22
| | | | | | | | | | | | | | | | | | | Once upon a time usbdev_status was created for the ft2232 programmer. Its IDs are semantically different to pcidev_status because they indicate USB instead of PCI IDs, but apart from that both data structures are equal. This change makes life easier for everything involved in handling and printing the status of devices that is noted in those structures by combining them into dev_entry. It is still possible to distinguish between PCI and USB devices indirectly by using the struct programmer's type field. Also, add a programmer column to the PCI and USB devices lists. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refactor PCI and USB device status printing.stefanct2012-12-271-14/+27
| | | | | | | | | | | | | | | | | To be able to get rid of lots of #ifdefs and centralize programmer-specific data more... - introduce two new fields to struct programmer_entry, namely enum type (OTHER, USB, PCI) and union devs (pcidev_status, usbdev_status or char *note). - use those fields to generate device listings in print.c and print_wiki.c. Bonus: add printing of USB devices to print_wiki.c and count supported PCI and USB devices. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add general programmer sanity checks.stefanct2012-12-261-3/+1
| | | | | | | | | And remove the completely unused vendor field. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix flashrom running on boards with coreboot.stefanct2012-09-241-1/+1
| | | | | | | | | | | | | | In r1577 we removed the discrimination of coreboot IDs and user-specified mainboards. The problem is that the board enable code required to find a board enable if either of these model strings were set. Therefore boards running coreboot that do not need a board enable failed to execute flashrom since then. This patch fixes this by handling coreboot IDs and user-supplied IDs differently again. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1605 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix compilation with MinGW.stefanct2012-09-011-0/+2
| | | | | | | | | | This was broken since r1557 when we got rid of some exit calls, but returned -1 instead which is not a valid HANDLE value. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make struct flashchip a field in struct flashctx instead of a complete copy.hailfinger2012-08-251-1/+1
| | | | | | | | | | | | | All the driver conversion work and cleanup has been done by Stefan. flashrom.c and cli_classic.c are a joint work of Stefan and Carl-Daniel. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix VIA VX*** support.stefanct2012-08-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | Helge Wagner's patch that added VIA VX900 chipset support made me look closer at the datasheets which led to some concise documentation about newer VIA chipsets: http://flashrom.org/VIA Based on that this patch adds full support for VX800/VX820, VX855/VX875 and VX900, including SPI and LPC. VT8237S was not changed (SPI support only) because there is no public datasheet and it is not clear how to distinguish between LPC and SPI strapping and investigations in (NDAed) documents have not brought up anything conclusively. enable_flash_vt823x could probably be enhanced too due to various ignored LPC options of the chipset. Signed-off-by: Helge Wagner <Helge.Wagner@ge.com> Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Tested-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Refactor the -p internal:mainboard handling.stefanct2012-08-201-6/+4
| | | | | | | | | | | | | | | | This patch gets rid of some global variables and makes lots of bits along the code path that control the board enable execution more generic and clearer. From now on flashrom aborts on a few more occasions that should be safer for the user. For example it aborts if the enable function for the specified mainboard (enable) can not be found. Parts of the board_match_cbname refactoring were done by Carl-Daniel. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move show_id to where it belongs.stefanct2012-08-111-3/+1
| | | | | | | | | And remove the unused force parameter. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Portability fixes and cleanupshailfinger2012-08-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move Mac OS X IOKit/DirectHW availability checks in the Makefile from compiler check to pciutils check. Print the compiler error messages for feature detection. Add DOS libpci in the Makefile includes only if a PCI-based programmer was requested. Restrict mmap usage in ich_descriptors_tool to Unix style systems. Build ich_descriptors_tool with the correct .exe extension on DOS/Windows. Build ich_descriptors_tool by default on x86. (Patch by Stefan Tauner) Print the Windows version instead of "unknown machine" on Windows. Don't #define our own __DARWIN__, use the standard OS X detection method. Update the README. Add more generated files to svn:ignore Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Introduce enum test_state.stefanct2012-07-281-5/+5
| | | | | | | | | | | | | | | | Previously boards in the wiki were tagged either as working or as known bad. But we added support to various boards via board enables that were then never tested because the owners have not reported back. This can now be tagged with NT and is shown appropriately. Also, the underlying data structure indicating state was converted from macros to an enum while preserving original integer values and is used for programmers and chipsets too. Signed-off-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@student.tuwien.ac.at> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Automatically release I/O permissions on shutdown.hailfinger2012-07-211-2/+1
| | | | | | | | | | | | | | | | | | | | | | get_io_perms() is renamed to rget_io_perms() and automatically registers a function to release I/O permissions on shutdown. Actually release I/O permissions on Solaris and iopl()-supporting operating systems like Linux. This patch fixes quite a few programmers which forgot to release I/O permissions on shutdown, and it simplifies the shutdown and error handling code for all others. Do not call exit(1) if I/O permissions are denied and return an error instead. This part of the patch was written by Niklas Söderlund. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Signed-off-by: Niklas Söderlund <niso@kth.se> Acked-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@1551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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