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* Add support for parallel flash on Dr. Kaiser PC-Waechter PCI devices.uwe2009-09-021-1/+2
| | | | | | | | | | | | | | | | The vendor sold different designs under that name, the patch works with the one that has an Actel FPGA as PCI-to-Flash bridge. The Flash chip is a "Macronix MX29F001B" (128 KB, parallel) soldered directly to the PCB. Flash operations (PROBE, READ, ERASE, WRITE) work as expected. Signed-off-by: TURBO J <turboj@gmx.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Use a common parameter variable for all programmers. This allows us tohailfinger2009-08-121-2/+2
| | | | | | | | | | | reduce #ifdef clauses a lot if we compile out some programmers completely. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@679 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Releasing IO permissions was done by hand everywhere. Use a properhailfinger2009-08-091-7/+1
| | | | | | | | | | | abstraction. Kill unneeded #include statements. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for the AMD Am29F010A/B chips.uwe2009-06-191-0/+1
| | | | | | | | | | | | | | Also, add support for the Silicon Image 3112(A) SATA controller. Both have been tested by Andrew Morgan <ziltro@ziltro.com> on hardware and work fine. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Andrew Morgan <ziltro@ziltro.com> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Only probe for chips with compatible bus protocols.hailfinger2009-06-011-0/+2
| | | | | | | | | | | | | | | | | | | It doesn't make sense to probe for SPI chips on a LPC host, nor does it make sense to probe for LPC chips on a Parallel host. This change is backwards compatible, but adding host protocol info to chipset init functions will speed up probing. Once all chipset init functions are updated and the Winbond W29EE011 and AMIC A49LF040A chip definitions are updated, the W29EE011 workaround can be deleted as the W29/A49 conflict magically disappears. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Tested on real hardware and Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix warning in satasii.c when compiling with gcc 4.4.0.uwe2009-05-311-1/+1
| | | | | | | | | Signed-off-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* A bunch of output beautifications and improvements, as well as docoxygene2009-05-221-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | fixes: - Update manpage, we now report supported boards via -L. - Add some missing escaping for '-' characters in the manpage. - Shorten some of the really long device names, so that -L output looks nicer. - Display a "table header" for all entries/columns in -L output. - Make -L output tabular for all lists for better readability. - Do not print "unknown XXXX SPI chip" entries in -L output. - And random other cosmetics... Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* The Silicon Image PCI0680 has bit 26 marked as reserved, so don't use it.uwe2009-05-201-2/+2
| | | | | | | | | Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Mark the Silicon Image PCI0680 Ultra ATA-133 controller as working.uwe2009-05-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | I tested identify, read, write, erase, verify successfully, HOWEVER, this will only work (at least on my card) after de-soldering the soldered-on PLCC32 one-time programmable (OTP) chip (Holtek HT27C010) and soldering on a (re-)programmable flash ROM chip or a socket. Example: http://www.coreboot.org/File:Sii_controller1.jpg http://www.coreboot.org/File:Sii_controller2.jpg The OTP chip which came on my card does not react to the standard JEDEC identify/read/write/erase commands anymore, so if all other such PCI0680 controllers which are around also have the same OTP chip (that's not necessarily the case), they cannot be used as "external programmer" in flashrom without the above mentioned modifications. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Factor out fallback_map/unmap, most external programmers don't needuwe2009-05-171-9/+0
| | | | | | | | | | | and special handling here (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Rename sata_sii.c to satasii.c for consistency (trivial).uwe2009-05-171-0/+124
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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