From 7bddb369910f3bf32fe33138b8e66cde3faa8922 Mon Sep 17 00:00:00 2001
From: uwe <uwe@2b7e53f0-3cfb-0310-b3e9-8179ed1497e1>
Date: Fri, 28 Nov 2008 21:36:51 +0000
Subject: Original v2 revision: 3779

Add support for the AMD/ATI SB600 southbridge SPI functionality.

This has been tested by Uwe Hermann on an RS690/SB600 board.

Signed-off-by: Jason Wang <Qingpei.Wang@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: https://code.coreboot.org/svn/flashrom/trunk@351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
 spi.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'spi.h')

diff --git a/spi.h b/spi.h
index c096dce..25ce297 100644
--- a/spi.h
+++ b/spi.h
@@ -80,6 +80,11 @@
 #define JEDEC_RDSR_INSIZE	0x01
 #define JEDEC_RDSR_BIT_WIP	(0x01 << 0)
 
+/* Write Status Enable */
+#define JEDEC_EWSR		0x50
+#define JEDEC_EWSR_OUTSIZE	0x01
+#define JEDEC_EWSR_INSIZE	0x00
+
 /* Write Status Register */
 #define JEDEC_WRSR		0x01
 #define JEDEC_WRSR_OUTSIZE	0x02
-- 
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